Methods and systems for digital dither

Details Methods and systems for digital dither Methods and systems for digital dither

2001-09-12

2003-06-10

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

C341S155000, C341S143000

Reexamination Certificate

active

06577257

ABSTRACT:

STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to data converters and, more particularly, to multi-bit analog-to-digital data converters such as delta-sigma modulators and, more particularly, to digital dither in data converters.
2. Background Art
A common limitation in the performance of audio analog delta-sigma modulators is quantization noise, including idle-channel noise. With small input amplitudes, performance is typically degraded by limit cycles in the modulator loop. The quantization noise spectra typically includes high-powered spectral tones at frequencies close to fs/2, where fs is a sampling rate of the modulator. There are two common causes for these tones to fold into the signal passband and degrade the performance of the analog delta-sigma modulator. One cause is due to interfering digital signals which couple onto the reference voltage for the delta-sigma modulator. When these interfering digital signals couple onto the reference voltage they intermodulate with the high-powered spectral tones and cause them to fold into the passband. For this reason analog delta-sigma modulators are sensitive to coupled digital noise. The second common cause of for the idle tones to fold into the signal passband is due to nonlinearities in the analog signal processing path in the analog delta-sigma modulator. In the presence of these nonlinearities the idle tones typically intermodulate with each other, causing them to fold into the signal passband. This results in audible tones that are often detectable by the human ear. Accordingly, it is desireable to reduce the amplitude of the idle-tones near fs/2. Quantization noise is described in “Delta-SigmaData Converters, Theory, Design, and Simulation,” edited by Norsworthy et al., IEEE Press, 1997, ISBN 0-7803-1045-4, incorporated herein by reference in its entirety.
A conventional solution to quantization noise in an analog delta-sigma modulator is to apply analog dither, or noise, in the modulator loop. For example, U.S. Pat. No. 5,055,846, entitled “Method of Tone Avoidance in Delta-Sigma Converters,” incorporated herein by reference in its entirety, appears to teach applying analog dither to an input of a quantizer and reducing the input signal to a very low level to reduce the signal-to-noise ratio of the signal. The resulting noisy input signal is applied to the input of a comparator in a single-bit analog delta-sigma modulator loop. The increased noise level in this signal acts as analog dither and helps to break up the spectral tones in the delta-sigma modulator.
The technique utilized in U.S. Pat. No. 5,055,846 is not suitable for use in a multi-bit analog delta-sigma modulator loop because performance is limited by errors in the thresholds of the quantizer. In a single-bit delta-sigma modulator a single comparator is used with the threshold set equal to zero. In this case comparator offset does not effect performance. In a multi-bit delta-sigma modulator the quantizer thresholds should be reduced in proportion to the reduction of signal amplitude. The quantizer thresholds should be placed very close together if the signal preceding the quantizer is attenuated. Inaccuracies in the quantizer thresholds cause an increase in the quantization error. This degrades the modulator performance.
What is needed are methods and systems for applying dither in analog-to-digital data converters, such as multi-bit delta-sigma modulators.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to methods and systems for applying digital dither. In an embodiment, digital dither is applied in data converters such as, without limitation, delta-sigma modulators. For example, in a delta-sigma modulator that receives an analog input signal and includes a first path including a quantizer that outputs an m-level code, an n-level dithered digital feedback signal is generated from the m-level code. In an embodiment, m is greater than one. In an alternative embodiment, m is equal to 1. In an embodiment, n is less than m. In an alternative embodiment, n is greater than m. The n-level dithered digital feedback signal is converted to an analog feedback signal and fed back to a second path of the delta-sigma modulator.
In an embodiment, the dithered digital feedback signal is generated from one or more portions of the m-level code. For example, in an embodiment, the m-level code is an m-bit signal, such as a thermometer coded signal, and the dithered digital feedback signal is generated by selecting between sub-sets of bits from the m-bit code. In an example embodiment, n equals m−1, a first sub-set of n-bits includes bits zero through m−2 of the m-bit signal, and a second sub-set of bits includes bits
1
through m−1 of the m-bit signal. In another example embodiment, m is an even integer, n equals m divided by 2, a first sub-set of n-bits includes even bits of the m-bit signal, and a second sub-set of bits includes odd bits of the m-bit signal.
In an embodiment, the dithered digital feedback signal is generated in inverse proportion to an amplitude of the input analog signal and/or the m-level code.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.


REFERENCES:
patent: 4914439 (1990-04-01), Nakahashi et al.
patent: 4937576 (1990-06-01), Yoshio et al.
patent: 4968987 (1990-11-01), Naka et al.
patent: 5055846 (1991-10-01), Welland
patent: 5329282 (1994-07-01), Jackson
patent: 5404142 (1995-04-01), Adams et al.
patent: 5406283 (1995-04-01), Leung
patent: 5684482 (1997-11-01), Galton
patent: 5835038 (1998-11-01), Nakao et al.
patent: 5986512 (1999-11-01), Ericksson
Delta-Sigma Data Converters Theory, Design, and Simulation, (Steven R. Norsworthy, et al. ed., IEEE Press Marketing) (1997).
Brooks, Todd L., et al., U.S. patent application No. 09/949,807, titled “Method and Apparatus for Mismatched Shaping of an Oversampled Converter,” filed on Sep. 12, 2001).
Brooks, Todd L., et al., U.S. patent application No. 09/949,815, titled “Method and Apparatus for Mismatched Shaping of an Oversampled Converter,” filed on Sep. 12, 2001).

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