Methods and systems for computer aided design of 3D...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S100000, C716S101000, C716S102000, C716S103000, C716S104000, C716S110000, C716S111000, C716S118000, C716S119000, C716S126000

Reexamination Certificate

active

08032857

ABSTRACT:
Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

REFERENCES:
patent: 4272880 (1981-06-01), Pashley
patent: 4489478 (1984-12-01), Sakurai
patent: 4612618 (1986-09-01), Pryor et al.
patent: 5109479 (1992-04-01), Williams
patent: 5201035 (1993-04-01), Stytz et al.
patent: 5825660 (1998-10-01), Cagan et al.
patent: 6355501 (2002-03-01), Fung et al.
patent: 6465892 (2002-10-01), Suga
patent: 6525415 (2003-02-01), Koyanagi et al.
patent: 6574360 (2003-06-01), Berdardini et al.
patent: 6727517 (2004-04-01), Chan et al.
patent: 6741198 (2004-05-01), McIlrath
patent: 6875671 (2005-04-01), Faris
patent: 6881994 (2005-04-01), Lee et al.
patent: 6943067 (2005-09-01), Greenlaw
patent: 7263674 (2007-08-01), Lorenz
Das, Shamik, “Design Automation and Analysis of Three-Dimensional Integrated Circuits”, Massachusetts Institute of Technology, May 2004, 176 pages.
“Masks Automatically,” Smithsonian National Museum of American History, Science Service, CD 1967051, E&MP 68.001.
Infante, B., et al, “An Interactive Graphics System for the Design of Integrated Circuits,” 15th Conference on Design Automation, Jun. 1978, pp. 182-187.
Fairbairn, D.G., Rowson, J.A., “ICARUS: An Interactive Integrated Circuit Layout Program,” 15th Conference on Design Automation, Jun. 1978, pp. 188-192.
Edmondson, T.H., Jennings, R.M., “A Low Cost Hierarchical System for VLSI Layout and Verification,” 18th Conference on Design Automation, Jun. 1981, pp. 505-510.
Daniel, M.E., Gwyn, C.W., “CAD Systems for IC Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 1, Jan. 1982, pp. 2-12.
Arnold, M.H., Ousterhout, J.K., “Lyra: A New Approach to Geometric Layout Rule Checking,” 19th Conference on Design Automation, Jun. 1982, pp. 530-536.
Heilweil, M.F., “Technology Rules—The Other Side of Technology Dependent Code,” 20th Conference on Design Automation, Jun. 1983, p. 389.
Von Ehr, G.J., “Position Paper: Role of Technology Design Rules in Design Automation,” 20th Conference on Design Automation, Jun. 1983, p. 395.
Ousterhout, J.K., et al, “Magic: A VLSI Layout System,” 21st Conference on Design Automation, Jun. 1984, pp. 152-159.
Ousterhout, J.K., “The User Interface and Implementation of an IC Layout Editor,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 3, Issue 3, Jul. 1984, pp. 242-249.
Smith, P.; Daniel, S., “The VIVID System Approach to Technology Independence: the Master Technology File System,” 22nd Conference on Design Automation, Jun. 1985, pp. 76-81.
Harter, A.C., Three-Dimensional Integrated Circuit Layout (Distinguished Dissertations in Computer Science), Cambridge University Press, Nov. 1991.
McIlrath, L.G. and Zavracky, P.M., “Architecture for Low-Power Real-Time Image Analysis using 3D Silicon Technology,” Proceedings of SPIE AeroSense 1998, vol. 3362, Aug. 1998, pp. 184-195.
Subramanian, V., et al, “Low-Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFT's for Vertical Integration Applications,” IEEE Electron Device Letters, vol. 20, No. 7, Jul. 1999, pp. 341-343.
Burns, J. A., et al, “Three-Dimensional Integrated Circuits for Low-Power, High Bandwidth Systems on a Chip,” Proceedings of the 2001 IEEE International Solid State Circuits Conference, Feb. 2001, pp. 268-269, 453.
Koyanagi, M., et al, “Neuromorphic vision chip fabricated using three-dimensional integration technology,” Proceedings of the 2001 IEEE International Solid State Circuits Conference, Feb. 2001, pp. 270-271, 454.
Chiricescu, S., et al, Design and analysis of a dynamically reconfigurable three-dimensional FPGA, IEEE Transactions on Very Large Scale Integration Systems, vol. 9, No. 1, Feb. 2001, pp. 186-196.
Banerjee, K., et al, “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration,” Proceedings of the IEEE, vol. 89, No. 5, May 2001, pp. 602-633.
McIlrath, L.G., “High Performance, Low Power Three-Dimensional Integrated Circuits for Next Generation Technologies,” Proceedings 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, Sep. 2002.
Qun, G., et al, “Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling,” 2004 Symposium on VLSI Technology, Jun. 2004, pp. 96-97.
Hung, W.N.N., et al, “Routability checking for three-dimensional architectures,” IEEE Transactions on Very Large Scale Integration Systems, vol. 12, No. 12, Dec. 2004, pp. 1371-1374.
Koob, J.C., et al, “Design of a 3D Fully-Depleted SOI Computational RAM,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, No. 3, Mar. 2005, pp. 358-369.
Patti, R., “3D: Design to Volume—A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results,” 3D Architectures for Semiconductor Integration and Packaging Symposium, Jun. 2005.
Manimegalai, R., “Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines,” 18th International Conference on VLSI Design, 2005, pp. 451-456.
S. Das, A. Chandrakasan, R. Reif, “Three-dimensional integrated circuits: performance, design methodology, and CAD tools”, Proceedings IEEE Computer Society Annual Symposium on VLSI, 2003, Feb. 20-21, 2003, pp. 13-18.
S. M. Alam et al. “A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits.” IEEE Proc. of ISQED 2002.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods and systems for computer aided design of 3D... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and systems for computer aided design of 3D..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and systems for computer aided design of 3D... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4256606

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.