Methods and systems for adaptive receiver equalization

Details Methods and systems for adaptive receiver equalization Methods and systems for adaptive receiver equalization

2007-10-23

2007-10-23

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Equalizers

Automatic

C375S229000, C375S346000, C360S051000, C704S200000

Reexamination Certificate

active

09844283

ABSTRACT:
Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

REFERENCES:
patent: 5235671 (1993-08-01), Mazor
patent: 5396224 (1995-03-01), Dukes et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5550546 (1996-08-01), Noneman et al.
patent: 5554945 (1996-09-01), Lee et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5650954 (1997-07-01), Minuhin
patent: 5703905 (1997-12-01), Langberg
patent: 5757857 (1998-05-01), Buchwald
patent: 5768268 (1998-06-01), Kline et al.
patent: 5822143 (1998-10-01), Cloke et al.
patent: 5881107 (1999-03-01), Termerinac et al.
patent: 5881108 (1999-03-01), Herzberg et al.
patent: 5945862 (1999-08-01), Donnelly et al.
patent: 5949820 (1999-09-01), Shih et al.
patent: 5966415 (1999-10-01), Bliss et al.
patent: 6002279 (1999-12-01), Evans et al.
patent: 6005445 (1999-12-01), Katakura
patent: 6009534 (1999-12-01), Chiu et al.
patent: 6038269 (2000-03-01), Raghavan
patent: 6122336 (2000-09-01), Anderson
patent: 6134268 (2000-10-01), McCoy
patent: 6329859 (2001-12-01), Wu
patent: 6359486 (2002-03-01), Chen
patent: 6397048 (2002-05-01), Toda
patent: 6404525 (2002-06-01), Shimomura et al.
patent: 6498694 (2002-12-01), Shah
patent: 6509773 (2003-01-01), Buchwald et al.
patent: 6621862 (2003-09-01), Dabell
patent: 6791388 (2004-09-01), Buchwald et al.
patent: 2002/0012152 (2002-01-01), Agazzi et al.
patent: 2002/0039395 (2002-04-01), Buchwald et al.
patent: 2002/0044617 (2002-04-01), Buchwald et al.
patent: 2002/0044618 (2002-04-01), Buchwald et al.
patent: 2002/0080898 (2002-06-01), Agazzi et al.
patent: 2003/0086515 (2003-05-01), Reans et al.
patent: 2004/0212416 (2004-10-01), Buchwald et al.
patent: 0 483 439 (1992-05-01), None
patent: 0 515 074 (1992-11-01), None
patent: 0 805 447 (1997-11-01), None
patent: 0 909 035 (1999-04-01), None
patent: 1 006 697 (2000-06-01), None
patent: 1 139 619 (2001-10-01), None
patent: WO 01/29991 (2001-04-01), None
patent: WO 01/54317 (2001-07-01), None
patent: WO 01/65788 (2001-09-01), None
patent: WO 01/84702 (2001-11-01), None
patent: WO 01/84724 (2001-11-01), None
patent: WO 02/13424 (2002-02-01), None
patent: WO 02/071616 (2002-09-01), None
Buchwald, A. and Martin, K., “Integrated Fiber-Optic Receivers,” Kluwer Academic Publishers, 1994 (entire book submitted).
Sidiropoulos, S. and Horowitz, M., “A Semidigital Dual Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, IEEE, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.
International Search Report issued Jan. 24, 2002, for Appln. No. PCT/US01/13613, 7 pages.
International Search Report issued Apr. 11, 2002, for Appln. No. PCT/US01/13637, 2 pages.
Black, Jr., W. and Hodges, D., “Time Interleaved Converter Arrays,”IEEE Journal of Solid-State Circuits, IEEE, vol. SC-15, No. 6, Dec. 1980, pp. 1022-1029.
Conroy, C. et al., “An 8-b 85-MS/s Parallel Pipeline A/D Converter in 1-μm CMOS,”IEEE Journal of Solid-State Circuits, IEEE, vol. 28, No. 4, Apr. 1993, pp. 447-454.
Dally, W. and Poulton, J., “Transmitter Equalization for 4Gb/s Signalling,”Proceedings of Hot Interconnects IV, Palo Alto, CA, 1996, 10 pages.
Ellersick, W. et al., “A Serial-Link Transceiver Based on 8GSample/s A/D and D/A Converters in 0.25 μm CMOS,”IEEE International Solid-State Circuits Conference, IEEE, 2001, pp. 58-59 and 430.
Ellersick, W. et al., “GAD: A 12-GS/s CMOS 4-bit A/D Converter for an Equalized Multi-Level Link,”Symposium on VLSI Circuits Digest of Technical Papers, 1999, pp. 49-52.
Eklund, J-E. and Gustafsson, F., “Digital Offset Compensation of Time-Interleaved ADC Using Random Chopper Sampling,”IEEE International Symposium on Circuits and Systems, IEEE, May 28-31, 2000, pp. III-447 thru III-450.
Fu, D. et al., “A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,”IEEE Journal of Solid-State Circuits, IEEE, vol. 33, No. 12, Dec. 1998, pp. 1904-1911.
Guizani, M. and Al-Ali, A., “PC-Compatible Optical Data Acquisition Unit,”Instrumentation and Measurement Technology Conference, IEEE, May 10-12, 1994, pp. 1099-1102.
Jenq, Y.-C., “Digital Spectra on Nonuniformly Sampled Signals: A Robust Sampling Time Offset Estimation Algorithm for Ultra High-Speed Waveform Digitizers Using Interleaving”Transactions on Instrumentation and Measurement, IEEE, vol. 39, No. 1, Feb. 1990, pp. 71-75.
Mason, R. and Taylor, J.T., “High-Speed Electro-Optic Analogue to Digital Converters,”IEEE International Symposium on Circuits and Systems, IEEE, 1993, pp. 1081-1084.
Niewczas, P. et al., “Error Analysis of an Optical Current Transducer Operating with a Digital Signal Processing System,”IEEE Transactions on Instrumentation and Measurement, IEEE, vol. 49, No. 6, Dec. 2000, pp. 1254-1259.
Petraglia, A. and Mitra, S., “Analysis of Mismatch Effects Among A/D Converters in a Time-Interleaved Waveform Digitizer,”IEEE Transactions on Instrumentation and Measurement, IEEE, vol. 40, No. 5, Oct. 1991, pp. 831-835.
Agazzi, O.,A Link Model for Equalized Optical Receivers, IEEE 802.3ae Equalization Ad Hoc Group, Mar. 11, 2001, 30 pages.
Agazzi, O. et al.,DSP-Based Equalization for Optical Channels: Feasibility of a VLSI Implementation, IEEE 802.3ae, New Orleans, Sep. 12-14, 2000, 39 pages.
Agazzi, O. et al.,Interim Observations on Multimode Optical Channels, IEEE 802.3ae—Equalization Ad Hoc, Tampa, Nov. 5, 2000, 29 pages.
Agazzi, O. et al.,Measurements of DMD-Challenged Fibers at 3.125Gb/s, IEEE 802.3ae Equalization Ad Hoc, Jan. 10, 2001, 33 pages.
Agazzi, O. and Lenosky, T., “Measurement on Non-Stationarity of 10 Gb/s Multimode Fiber Links,” Nov. 24, 2000, 5 pages.
Agazzi, O.,10 Gb/s PMD Using PAM-5 Modulation, IEEE 802.3, Dallas, Jan. 18-20, 2000, 19 pages.
Fettweis, G., “Parallel Viterbi Algorithm Implementation: Breaking the ACS-Bottleneck,”IEEE Transactions on Communications, IEEE, vol. 37, No. 8, Aug. 1989, pp. 785-790.
Forney, Jr., G.D., “The Viterbi Algorithm,”Proceedings of the IEEE, IEEE, vol. 61, No. 3, Mar. 1973, pp. 268-278.
Frazier, H.,IEEE 802.3 Higher Speed Study Group, IEEE 802.3 HSSG, Kauai, Hawaii, Nov. 9, 1999, 24 pages.
Giaretta, G. and Lenosky, T.,Adaptive Equalization of DMD Challenged Multimode Fiber at 1300 mm, IEEE P802.3ae Plenary, Mar. 11, 2001, 10 pages.
Hatamian, M. et al., “Design Considerations for Gigabit Ethernet 1000Base-T Twisted Pair Transceivers,”IEEE 1998 Custom Integrated Circuits Conference, IEEE, 1998, pp. 335-342.
Isaacs, M et al.,Measurements of Fiber Responses at 5 Gb/s Data Rate Using 850nm VCSELs, IEEE 802.3ae Equalization Ad Hoc, Mar. 11, 2001, 18 pages.
Kanno, N. and Ito, K., “Fiber-Optic Subcarrier Multiplexing Video Transport Employing Multilevel QAM,”IEEE Journal on Selected Areas in Communications, IEEE, vol. 8, No. 7, Sep. 1990, pp. 1313-1319.
Kasper, B.L., “Equalization of Multimode Optical Fiber Systems,”The Bell System Technical Journal, American Telephone and Telegraph Company, vol. 61, No. 7, Sep. 1982, pp. 1367-1388.
Kasturia, S. and Winters, J.

Affiliated with

Also associated with

Rating

Methods and systems for adaptive receiver equalization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and systems for adaptive receiver equalization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and systems for adaptive receiver equalization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3848402