Methods and system for predecoding instructions in a superscalar

Details Methods and system for predecoding instructions in a superscalar Methods and system for predecoding instructions in a superscalar

1995-09-20

1998-10-27

Donaghue, Larry D.

395393, 395389, G06F 930

Patent

active

058288953

ABSTRACT:
In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction belongs is selected from multiple instruction categories. Types of data processing system resources required for instruction execution and a quantity of each type of resource required are determined. Thereafter, a plurality of decode bits are calculated, wherein the decode bits represent a particular instruction category in which the instruction belongs and the type and quantity of each data processing system resource required for execution of the instruction. Thereafter, the instruction and the predecode bits are stored in instruction cache. The predecode bits enable the dispatch unit to efficiently, and without fully decoding the instruction at dispatch time, select an execution unit for executing the instruction and determine if the data processing system resources required for execution of the instruction are available before the dispatch unit dispatches the instruction.

REFERENCES:
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4722050 (1988-01-01), Lee et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5131086 (1992-07-01), Circello et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5337415 (1994-08-01), Delano et al.
patent: 5560028 (1996-09-01), Sachs
IBM Technical Disclosure Bulletin, vol. 14, No. 12, May 1972, pp. 3599-3611, "Instruction Sequencing Control".
IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, pp. 134-135, "Improved Condition Code and Branch Handling for Model 91-Like Implementation of the IBM System/370 Architecture".
IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982, pp. 136-137, "New Condition Code and Branch Architecture for High Performance Procesors".
Barreh et al.; "The Power2 Processor" Mar/1994; IEEE.
Minagawa et al. "Pre Decoding Mechanism for Superscalar Architecture" IEEE; 1991.

Affiliated with

Also associated with

Rating

Methods and system for predecoding instructions in a superscalar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and system for predecoding instructions in a superscalar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and system for predecoding instructions in a superscalar will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1621990