Patent
1994-10-21
1996-09-03
Robertson, David L.
395467, 395471, 395473, G06F 1300
Patent
active
055532659
ABSTRACT:
Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.
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Abato Richard P.
Greer William R.
Herring Christopher M.
International Business Machines - Corporation
Robertson David L.
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