Methods and structures for relaxation of strained layers

Details Methods and structures for relaxation of strained layers Methods and structures for relaxation of strained layers

2008-12-22

2011-11-01

Garber, Charles (Department: 2812)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

C438S062000, C438S455000, C438S974000, C257SE21213, C257SE29089

Reexamination Certificate

active

08048693

ABSTRACT:
The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that the reflow of the first and the second low-viscosity layers permits the strained-material layer to at least partly relax.

REFERENCES:
patent: 4994867 (1991-02-01), Biegelsen
patent: 5391257 (1995-02-01), Sullivan et al.
patent: 5670411 (1997-09-01), Yonehara et al.
patent: 5965939 (1999-10-01), Kim et al.
patent: 6214733 (2001-04-01), Sickmiller
patent: 6406795 (2002-06-01), Hwang et al.
patent: 6794276 (2004-09-01), Letertre et al.
patent: 7018909 (2006-03-01), Ghyselen et al.
patent: 7273798 (2007-09-01), Lester et al.
patent: 7282381 (2007-10-01), Feltin et al.
patent: 7585792 (2009-09-01), Celler
patent: 7736935 (2010-06-01), Faure et al.
patent: 2003/0064535 (2003-04-01), Kub et al.
patent: 2004/0192067 (2004-09-01), Ghyselen et al.
patent: 2004/0253792 (2004-12-01), Cohen et al.
patent: 2005/0250294 (2005-11-01), Ghyselen et al.
patent: 2006/0094140 (2006-05-01), Inoguchi et al.
patent: 2006/0128117 (2006-06-01), Ghyselen et al.
patent: 2006/0175608 (2006-08-01), Celler
patent: 2006/0205180 (2006-09-01), Henley et al.
patent: 2006/0211219 (2006-09-01), Henley et al.
patent: 2007/0048975 (2007-03-01), Chen et al.
patent: 2007/0069225 (2007-03-01), Krames et al.
patent: 2007/0072324 (2007-03-01), Krames et al.
patent: 2007/0241353 (2007-10-01), Taki
patent: 2007/0278622 (2007-12-01), Lester et al.
patent: 2007/0298549 (2007-12-01), Jurczak et al.
patent: 2008/0113496 (2008-05-01), Keller et al.
patent: 2008/0169483 (2008-07-01), Kasai et al.
patent: 2009/0050917 (2009-02-01), Nakagawa et al.
patent: 2009/0261344 (2009-10-01), Celler
patent: 2010/0032793 (2010-02-01), Guenard et al.
patent: 0651439 (1995-05-01), None
patent: 0 858 110 (1998-08-01), None
patent: 1378591 (2004-01-01), None
patent: 1 671 361 (2007-04-01), None
patent: 1901345 (2008-03-01), None
patent: 2775121 (1999-08-01), None
patent: 2895420 (2007-06-01), None
patent: 2895562 (2007-06-01), None
patent: WO 2004/077552 (2004-09-01), None
Notice of Allowance dated Feb. 24, 2010, U.S. Appl. No. 12/341,806, filed Dec. 22, 2008.
Feng et al., “Stress Generation and Relaxation during Film Heteroepitaxy on a Compliant Substrate with a Viscoelastic Glass Interlayer,” Mat. Res. Soc. Symp. Proc., 696:N3.19.1-N3.19.6 (2002).
Hansen et al., “Development of a glass-bonded compliant substrate,” Journal of Crystal Growth, 195:144-150 (1998).
Moran et al., “Kinetics of Strain Relaxation in Semiconductor Films Grown on Borosilicate Glass-Bonded Substrates,” Journal of Electronic Materials, 30(7):802-806 (2001).
European Search Report for EP08290757.7 dated Mar. 16, 2009.
Haizhou Yin et al., “Fully-depleted Strained-Si on Insulator NMOSFETs without Relaxed SiGe Buffers”, IEDM International Electron Devices Meeting, , pp. 03-53-03-56 (2003).
C. X. Peng et al., “Influence of GaN polarity and intermediate-temperature buffer layers on strain relaxation and defects”, Physica Bvol. 391, No. 1, pp. 6-11 (2007).
European Search Report for EP 08 29 0759 dated Apr. 14, 2009.
Hobart, K.D. et al., “Compliant Substrates: A Comparative Study of the Relaxation Mechanisms of Strained Films Bonded to High and Low Viscosity Oxides”, Journal of Electronic Materials, vol. 29, No. 7, pp. 897-900 (2000).
L. Di Cioccio et al., “III-V Layer Transfer Onto Silicon and Applications”, Phys. Stat. Sol., vol. (a) 202, No. 4, pp. 509-515 (2005).
M. Kostrzewa et al, “Feasibility of Strain Relaxed InAsP and InGaAs Compliant Substrates”, pp. 437-440 (2003).
P. M. Mooney et al., “Elastic Strain Relaxation in Free-Standing SiGe/Si Structures”, Applied Physics Letters, vol. 84, No. 7, pp. 1093-1095 (2004).
Haizhou Yin et al., “Buckling Suppression of SiGe Islands on Compliant Substrates”, Journal of Applied Physics, vol. 94, No. 10, pp. 6875-6882 (2003).
Haizhou Yin et al., “Strain Relaxation of SiGe Islands on Compliant Oxide”, Journal of Applied Physics, vol. 91, No. 12, pp. 9716-9722 (2002).
International Search Report, PCT/EP2009/004790, mailed Sep. 23, 2009.
U.S. Appl. No. 13/055,123, filed Jan. 20, 2011.
U.S. Appl. No. 13/056,572, filed Jan. 28, 2011.

Affiliated with

Also associated with

Rating

Methods and structures for relaxation of strained layers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and structures for relaxation of strained layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and structures for relaxation of strained layers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4310877