Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
2001-11-27
2004-05-25
Miska, Vit W. (Department: 2841)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C368S120000, C327S141000, C327S145000, C327S161000, C327S261000, C327S291000, C327S295000
Reexamination Certificate
active
06741522
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital circuit designs utilizing delay lines for phase offset generation and comparison and more specifically relates to use of higher frequency clocks applied to a master delay lines used for calibrating associated slave delay lines. The higher frequency clock used with the master delay line permits shortening of the master delay line thereby improving its accuracy.
2. Discussion of Related Art
In most present in digital electronic circuits, clock signals are used to control and synchronize operation of the digital components to achieve the intended purpose, Clock signals inherently have an associated clock frequency and clock period. In a variety of digital circuit applications, it is necessary to generate desired phase offset relationships between signals associated with a common clock. For example, a first signals may be generated using a first phase relationship to a basic system clock while a second related signal may be generated with a second phase relationship from either the first signal or the common basic system clock. Similarly, it is often required that phase relationships be measured to detect relevant or desired phase relationships between two signals relative to a common system clock.
In generating or detecting such phase relationships relative to a basic system clock, it is common to use delay lines to establish a desired phase relationship delay between associated edges of the related digital signals. Such delay lines are comprised of a plurality of sequential delay elements each of which delays an input signal a predetermined fixed fraction of a clock period of the basic system clock from which the phase relationships are to be established. Each delay element of a plurality of delay elements is chained to a subsequent element (other than the final delay element). An appropriate number of such delay elements are chained together to create the desired delay necessary for achieving the desired phase relationship between a first signal and a second signal. For example, the first signal may be passed directly from the generating source to an intended recipient component whereas the second related signal is passed from its point of generation through an appropriate number of delay elements of a delay line and then on to its intended recipient component. The second signal being so delayed provides the desired phase relationship between the first and second signal.
Each delay element in such a chain of delay elements comprising a delay signal line has some inherent variability in its accuracy for imposing the specified delay amount. The design of digital circuits and the eventual layout and fabrication of a circuit having a delay line comprising multiple delay elements may impose further inaccuracies in the delay timing generated by such a delay line. For example, the layout of the delay elements in a particular delay line may introduce significant propagation delay between the chained delay elements of the delay line thus affecting the accuracy of the entire delay line.
It is generally known in the art to carefully layout and design circuits including delay line components so as to minimize the potential additional inaccuracy in such delay lines. Careful layout of a circuit design can help minimize propagation delays in a delay line. However, such care is difficult and often impractical in the design and fabrication of modern, complex integrated circuits. Further, the number of such delay lines in a complex integrated circuit may be substantial thereby further complicating any efforts to carefully layout and fabricate the circuit design so as to minimize propagation delays within delay line components.
One known technique for improving delay line accuracy is to provide a single delay line using the same delay elements as other delay lines but for which extra care is taken in the layout and fabrication so as to minimize additional inaccuracies in that particular delay line signal path. Such a carefully designed and fabricated delay line is often referred to as a “master delay line” or “reference delay line.” The master delay line is then used in conjunction with calibration circuits to more precisely measure the delay required to achieve a particular desired phase relationship. Calibration information derived from such calibration circuits is then used in other operational delay lines within the circuit design to configure each operational delay line with reference to the more accurate master or reference delay line. These operational delay lines are often referred to as “slave delay lines” in that they are “slaved” to the master or reference delay line.
It remains a problem however to assure accuracy of even the master delay line. Even the most careful design layout and fabrication procedures may be inadequate to generate a highly precise master delay line. In particular, a long delay line (i.e., one comprised of a large number of delay elements) may entail unavoidable layout and fabrication problems. Regardless of the degree of care taken by the designer, a lengthy delay line may require compromises in circuit layout that may impose additional undesired inaccuracies in the master delay line.
It is evident from the above discussion that a need exists for methods and associated structure that provide additional accuracy in the design, layout and fabrication of master delay lines.
SUMMARY OF THE INVENTION
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing methods and structure for the design of a master delay line using a higher frequency clock as compared to the base system clock used for associated slave delay lines. Use of a higher frequency clock in design of the master delay line permits the master delay line to be shortened by comparison to a master delay line using the same clock frequency as its associated slave delay lines. By so reducing the number of delay elements in the master delay line through use of the higher frequency clock, the accumulated inaccuracies (also referred to as “static errors” or “static phase errors”) is further reduced. The shorter master delay line may be more carefully designed, laid out and fabricated to minimize static errors induced by delay line propagation delays.
Slave delay lines associated with functional components of the overall circuit design and calibrated to the master delay line of the present invention operate on a slower clock than that associated with the master delay line. The slave delay lines therefore include a scaling or gear factor to adjust the calibrated reference configuration information to timing parameters of the slower frequency clock signal.
It is common in present-day circuit designs that a number of clock signals are available within the circuit. In a particular area of the circuit design, operational delay lines (slave delay lines) often utilize a common clock as the basis for their signal delay generation for phase offset and sensing features. Other clocks are generally readily available within the circuit design including common integer multiples of the frequency of the base clock used in functional components of the circuit and associated with slave delay lines. In this sense, the methods and structure of the present invention are applicable in any digital design where slave delay lines are calibrated to a master delay line and where multiple clocks of varying frequencies are available within the circuit design.
In one particular exemplary preferred embodiment, a DDR (double data rate) SDRAM memory controller integrated circuit often has a clock running at double the frequency of a base clock used within the memory controller for clocking the external memory devices. Application of the methods and structure of the present invention within such a DDR SDRAM memory controller permits the master delay line to be designed based upon the double (2×) frequency clock while slave delay lines, typically utilizing identical delay elements and ca
LSI Logic Corporation
Miska Vit W.
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