Coded data generation or conversion – Analog to digital conversion followed by digital to analog...
Patent
1996-08-01
1998-09-15
Hoff, Marc S.
Coded data generation or conversion
Analog to digital conversion followed by digital to analog...
341159, H03M 100
Patent
active
058085734
ABSTRACT:
Analog-to-digital converter (ADC) output bits are partitioned in a way that simplifies the phase error calculations. The circuit architecture embeds the implementation of the phase error calculations in the analog-to digital-converter (ADC) to simplify the overall circuit implementation. Simplification of the phase error calculations allows a reduction in the complexity of the circuits needed to implement the phase-locked-loop (PLL) for recovering the sampling clock.
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Chern Jenn-Gang
Pan Tzu-Wang
Shih Shih-Ming
Hoff Marc S.
MacPherson Alan H.
NEC Electronics Incorporated
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