Methods and structure for improved high-speed TDF testing...

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage

Reexamination Certificate

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C324S076540, C324S076820

Reexamination Certificate

active

11061292

ABSTRACT:
Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher frequency PLL Clock. Gating Logic features and aspects within the integrated circuit may apply the PLL Clock signal to a TDF Clock signal when so directed by a TDF Enable signal from an external test system. The PLL Clock is applied to the TDF Clock signal path for precisely two clock pulses for use as a launch and capture pulse sequence for TDF testing at higher speeds than the external automated test system may achieve.

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patent: 2004/0239310 (2004-12-01), Oshima et al.
R. Press et al.; Heading Off Test Problems Posed By SOC; EETimes; Oct. 16, 2000; www.eetimes.com.

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