Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-07-10
2002-03-12
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S154000
Reexamination Certificate
active
06356126
ABSTRACT:
BACKGROUND OF THE INVENTION
A PLL is an electronic circuit which is widely used to generate highly stable signals for electronic and communication devices, such as wireless telephones and the like. More specifically, a PLL is used to control the frequency of a signal generated by a voltage controlled oscillator (“VCO”) or the like. VCOs are used in almost every communications device. For example, wireless telephones communicate with one another and with wireless networks using signals generated by VCOs embedded within such telephones. The signals generated by VCOs are then used to transmit voice and data messages.
Today's modem communication devices require that signals generated by a VCO be stable and accurate. That is, for a telephone to work properly, for a telephone to communicate with another wireless telephone or a wireless network a VCO's signal must be accurate (i.e., maintained within a narrow range).
Enter the PLL. A simplified, typical PLL circuit
100
is shown in FIG.
1
. As shown, a VCO
1
outputs a signal (referred to as “VCO
out-freq
”) along pathway
8
. This signal may be any frequency, but for the following example, it will be assumed to be in megahertz (“MHz”). This is a fair assumption considering the typical frequencies used by wireless devices. It should be understood that the present invention envisions frequencies in the MHz and gigahertz (“GHz”) range as well, however. That said, strictly speaking, the methods and devices envisioned by the present invention can utilize any frequency, not just MHz or GHz.
To insure that the signal output by the VCO
1
remains accurate, its output is also fed back to a MAIN counter
2
along pathway
9
a
. This counter
2
is designed to accept VCO
out-freq
and to divide this frequency down by an amount dictated by a MAIN counter setting to generate a “PM” signal
7
b
. The PM signal is one of two signals input into a phase detector
11
. The second signal is input from a reference counter (“REF counter”)
3
. The REF counter
3
also supplies a signal (“PR”)
7
a
along pathway
10
a
. The signal supplied by the REF counter
3
originates with a signal generator
5
which is adapted to output a signal whose frequency is maintained within a specific, narrow range. It can be said that the signal generator
5
acts as a reference source. That is, the output of the VCO
1
can be compared against the signal output from the signal generator
5
to make sure the frequency of the signal output by the VCO
1
stays within an acceptable range.
Backtracking somewhat, the REF counter
3
and MAIN counter
2
are adapted to divide down the frequencies of their respective inputs
9
a
,
9
b
such that:
PR
freq
=REF IN
freq
/REF
setting
(1)
and
PM
freq
=VCO
out-freq
/MAIN
setting
(2)
where PR
freq
is the frequency of the PR signal
7
a
output from the REF counter
3
; REF IN
freq
is the frequency of the signal
9
b
input from the signal generator
5
; REF
setting
is an amount that controls the “divide down” function of the REF counter
3
; PM
freq
is the frequency of the PM signal
7
b
output from the MAIN counter
2
; MAIN
setting
is an amount that controls the “divide down” function of the MAIN counter
2
; and VCO
out-freq
is the frequency of the signal input into the MAIN counter
2
from the VCO
1
along pathway
9
a.
In a typical PLL, the REF counter
3
and MAIN counter
2
settings are intentionally set so that the PR
freq
and PM
freq
are exactly equal. This implies:
REF IN
freq
/REF
counter setting
=VCO
out-freq
/MAIN
setting
. (3)
As shown in
FIG. 1
, the phase detector
11
is adapted to receive both the PR
7
a
and PM
7
b
signals. Thereafter, the phase detector
11
is further adapted to output a signal
7
c
based on the frequency and phase of the PR and PM signals
7
a
,
7
b
. For example, if the PR and PM signals have the same frequency and phase, the phase detector will not output a signal. As is known in the art, loop filter
6
typically comprises a capacitance whose stored charge maintains a constant voltage input into VCO
1
(i.e., “the loop is considered locked”). However, if the PR and PM signals
7
a
,
7
b
are not in agreement, the phase detector
11
is adapted to output an error signal to the charge pump
4
. Upon receipt of this error signal, the charge pump
4
is adapted to supply a necessary current to the loop filter
6
which in turn adjusts the voltage which is input into the VCO
1
. By changing the voltage input into the VCO
1
, the frequency of VCO
out-freq
is changed. This change in frequency is designed to “drive” or control the operation of the VCO
1
so that VCO
out-freq
remains stable. Said another way, the PLL is considered stable when the PR and PM signals agree in frequency and phase. When this occurs, VCO
out-freq
will be maintained at a stable, set value.
From equation (3), VCO
out-freq
can be defined as:
VCO
out-freq
=REF IN
freq
*MAIN
setting
/REF
counter setting
. (4)
As may be apparent from the discussion above, to insure that the correct adjustment is made to the VCO
1
, it was assumed that the MAIN and REF counters
2
,
3
were operating accurately. If either one or both of the counters are not operating accurately, then it will be difficult to correctly adjust the VCO
1
.
Many things may cause a MAIN or REF counter to output an inaccurate signal. Sometimes the counter becomes inoperative over time. More frequently, however, a counter is operating correctly but receives a signal (e.g., from a VCO or another source) which causes it to output an inaccurate signal. For example, design limitations may dictate that the MAIN counter
2
shown in
FIG. 1
will output a PM signal only after receiving a signal from the VCO
1
which is greater than a certain threshold. If the VCO output (which is input into the MAIN counter
2
) falls below this threshold, no PM signal will be output. In actuality, there is an upper and lower limit to this threshold such that only those signals falling within the range of signals between both limits will cause the MAIN counter
2
to output a PM signal. The lower limit is known as the “sensitivity” of a counter while the upper limit is known as the “saturation” of a counter.
On occasion, however, a signal falls just below or just above the limits of a counter. Sometimes these signals are so close to either limit that they trigger the counter to output a signal. These circumstances typically occur intermittently and are, for the most part, unpredictable. Nonetheless, to the extent possible, it is important to know when such circumstances might occur because once a counter has output an erroneous PM or PR signal it will adversely affect the ultimate frequency output by a VCO.
Realizing this, most manufacturers test REF and MAIN counters to determine whether they will produce miscounts when signals below, within or above the sensitivity and saturation limits are applied to the counters.
Up until now, however, the techniques used to test for such miscounts have been inadequate. Sometimes the techniques lack the ability to detect such intermittent miscounts. Other times, these techniques require additional circuitry. In each case, the techniques are “closed loop”. That is, the techniques require a MAIN counter to be connected to a VCO forming a closed loop.
Accordingly, it is desirable to provide for methods and devices for testing the operation of counters used in PLLs which are capable of detecting intermittent miscounts.
It is also desirable to provide for methods and devices for testing the operation of counters used in PLLs which do not require a closed loop.
Other desires, features and advantages of the present invention will become apparent to those skilled in the art from the following description taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
In accordance with the present invention there are provided methods and devices for testing the operation of MAIN and REF counters used in a PLL.
To test the operation
Anderson David L.
Gupta Naresh
Shewell Thomas L.
Strelchun Thomas F.
Cox Cassandra
Curtin John E.
Schutz James E.
Tran Toan
Troutman Sanders LLP
LandOfFree
Methods and devices for testing the operation of counters... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and devices for testing the operation of counters..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and devices for testing the operation of counters... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2818168