Data processing: measuring – calibrating – or testing – Measurement system – Dimensional determination
Reexamination Certificate
2002-04-18
2004-07-27
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Dimensional determination
C438S016000, C438S071000
Reexamination Certificate
active
06768965
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods and computer program products for characterizing a crystalline structure, such as a wafer and, more particularly, to methods and computer program products for characterizing a portion of the surface of a crystalline structure proximate the edge of the crystalline structure.
BACKGROUND OF THE INVENTION
Semiconductor wafers serve as the substrate for a wide variety of microelectronic and semiconductor devices (hereinafter generally referred to as “devices”). As such, wafers are formed of silicon, germanium or the like and are doped in a manner appropriate for the subsequent device fabrication. In order to properly fabricate devices upon the wafer, the wafer must meet increasingly stringent specifications that are generally promulgated by the device manufacturers. Among other things, these specifications define the permissible thickness of the wafer and the requisite flatness of the major surface of the wafer upon which the devices will be formed. Accordingly, wafer manufacturers and/or device manufacturers measure a number of parameters which define the size and shape of the wafer to either insure that the wafer meets specifications or to identify the parameter(s) that are out of tolerance.
Wafer inspection systems have therefore been developed by ADE Corporation and others, such as NewCreation Co., Ltd. of Komae, Japan. These commercially available wafer inspection systems measure a variety of parameters that define the thickness, flatness and taper of a wafer and can provide various displays of this data, either on a global basis across the entire surface of the wafer or on a more particularized basis for each of a plurality of sites across the surface of a wafer which will, in turn, support a respective device.
As a result of the relatively stringent specifications, wafer manufacturers have designed the various stages of wafer fabrication to ensure that a large percentage of the wafers meet or exceed the specifications. For example, the polishing processes for polishing the major surface of the wafers on which the devices will be formed have been designed with a goal of producing wafers that meet or exceed the specifications. Notwithstanding the careful design of the various stages of the wafer fabrication process, it has generally been difficult to fabricate wafers that both have a consistent thickness and a flat surface within those regions of the wafer proximate the wafer edge. Instead, many wafers suffer from either edge flip in which those portions of the wafer proximate the wafer edge have a greater thickness than more medial portions of the wafer, or edge roll in which those portions of the wafer proximate the wafer edge have a reduced thickness relative to medial portions of the wafer. In either situation, the portion of the wafer proximate the wafer edge is not flat in comparison the medial portions of the wafer. Edge flip and edge roll are attributable to a variety of factors throughout the wafer fabrication process, including the polishing process in which somewhat different forces may be applied to the regions of a wafer proximate the wafer edge than the medial portions of the wafer.
Traditionally, the specifications that govern wafer fabrication provided an exclusion for an annular region of the wafer proximate the wafer edge. Within the annular region of the wafer denoted by the edge exclusion, the wafer was not required to meet all of the specifications since it was not contemplated that devices would be fabricated within this annular region. Over time, the size of the edge exclusion has been reduced as device manufacturers have begun to fabricate devices closer to the edge of the wafer. While this reduction in the edge exclusion has been advanced by the manufacturers of a wide variety of devices, the manufacturers of dynamic random access memory (DRAM) devices are among those device manufacturers that have driven the reduction in permissible edge exclusion.
With the reduction and perhaps eventual elimination of the edge exclusion, wafer manufacturers must be capable of characterizing the portion of the wafer that is proximate the wafer edge to ensure that all useful portions of the wafer meet the specifications. As such, conventional wafer inspection systems collect the same type of data for the portion of the wafer proximate the wafer edge, such as the wafer thickness and flatness, as is collected for medial portions of the wafer. However, since wafer manufacturers generally have more difficulty ensuring that the portion of the wafer proximate the wafer edge meets the specifications, wafer manufacturers would typically like to conduct a more detailed analysis of the portion of the wafer proximate the wafer edge than more medial portions of the wafer. In this regard, wafer manufacturers may desire to conduct a more detailed analysis of the portion of the wafer proximate the wafer edge in order to better characterize the wafer, such as the profile of the wafer proximate the wafer edge for the device manufacturer so that the device manufacturer can appropriately fabricate devices upon this portion of the wafer. For example, device manufacturers may be able to fabricate devices upon the portion of the wafer proximate the wafer edge even if this portion of the wafer has a slight edge flip or edge roll so long as the device manufacturer can define the profile of the wafer proximate the wafer edge with enough specificity.
Moreover, wafer manufacturers may desire to further analyze the portion of a wafer proximate the wafer edge in order to gather information that will assist the wafer manufacturer in modifying or refining the wafer fabrication process in order to remedy any problems associated with bringing the portion of the wafer proximate the wafer edge into conformity with the specifications. For example, if wafer manufacturers can determine that even though the portion of the wafer proximate the wafer edge does not meet specifications, the portion of the wafer proximate the wafer edge consistently has an edge flip of approximately the same amount, the wafer manufacturer may be able to more readily adjust the fabrication process, such as the polishing steps, in order to reduce or eliminate the edge flip and to bring subsequent wafers into conformity with the specifications.
In addition to the inspection and characterization of a wafer, it is oftentimes desirable to inspect and characterize other types of crystalline structures. For example, an epitaxial layer may be deposited upon a wafer prior to device fabrication. Since an epitaxial layer is generally deposited upon a wafer, the epitaxial layer may exhibit the same variations in shape, particularly about the edge of the wafer, as presented by the underlying wafer. Although less pronounced that a wafer, an epitaxial layer may also have slight variations in thickness For the reasons described above in conjunction with a wafer, it would be desirable to inspect other types of crystalline structures, such as epitaxial layers, particularly about the edge thereof.
SUMMARY OF THE INVENTION
Methods and computer program products for analyzing a crystalline structure, such as a wafer, an epitaxial layer or the like, in more detail, including the portion of the crystalline structure proximate the edge, are provided. Among other things, the methods and computer program products of certain embodiments of the present invention determine the average thickness and the normalized profile of a crystalline structure in more detail than conventional techniques. Additionally, the method and computer program product of other embodiments of the present invention represent the profile proximate the edge of a crystalline structure with a pair of lines that are selected to permit the profile of the crystalline structure proximate the edge of the crystalline structure to be characterized in more detail. Further, the method of yet another embodiment of the present invention permits the average edge profile for a plurality of crystalline structures to be defined.
A
Martin Stephen L.
Oba Shigeru
Suzuki Yoshinori
SEH America Inc.
Walling Meagan S
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