Pulse or digital communications – Equalizers
Reexamination Certificate
1999-10-08
2003-04-08
Chin, Stephen (Department: 2734)
Pulse or digital communications
Equalizers
C375S232000, C375S233000, C333S018000
Reexamination Certificate
active
06546047
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to circuits and methods for conditioning a received signal, and, in particular, methods and circuits for determining an optimal code for an equalizer of a receiver.
2. Description of the Prior Art
There are several approaches in implementing a receive channel in a communication system using the analog approach (an example of such system is the receive channel for a 100TX Fast Ethernet transceiver).
FIG. 1
illustrates a traditional approach where the received signal is compensated by an equalizer
10
. The amplitude of the equalized signal is feed to a slicer
12
and an adaptation circuit
16
. The adaptation circuit
16
compares the equalized signal with a present reference voltage to determine an error signal. Base on the value of the error signal, the adaptation circuit can adjust the equalizer
10
to a different setting thereby changing the amount of the compensation to the incoming signal.
FIG. 2
a
illustrates an example of the frequency response of a received signal.
FIG. 2
b
illustrates the various taps (also referred to as codes) that may be selected and provided by an equalizer in compensating the received signal.
FIG. 2
c
illustrates the desired result.
The slicer
12
slices the equalized signal with a pre-set voltage that matches the adaptation reference voltage and the sliced signal is then passed to the clock recovery circuit
14
. The clock recovery circuit locates the data edge within a time window, locks to the data, and constantly adjusts itself to adapt to the incoming (equalized and sliced) signal. However, if the incoming signal has excessive jitters, the clock recovery circuit may lose the lock on the data.
There are several causes of jitter in this system. First, if the equalized signal mismatches with the fixed slice level, it can cause pulse width distortion of the sliced signal, which translates to clock jitter. Second, the transmitter, communication channel, cable, transformer, etc. can also causes excessive jitter and noise. If the combined jitter becomes large enough, the data edge may no longer be located within the time window centered by the recovery clock and the clock recovery circuit will then lose lock on the data and the data will lost. From the receiver side, there is little that can be done with the second cause of jitter. To reduce the jitter caused by the first cause, in the traditional system, the equalized signal is monitored and the setting for the equalizer is altered accordingly to minimize the error signal when compared against the provided reference signal.
The traditional system is conceptually simple. However, this system heavily relies on amplitude information and it is therefore sensitive to voltage, process, and temperature variation. Especially when the supply voltage becomes lower and lower, it is difficult to ensure that the adaptation circuit can adapt to a working code in all comer conditions.
It is therefore desirable to have a solution that allows the receiver to tolerate and operate reliably under extreme conditions and minimize the effect from voltage, process, and temperature variations.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide reliable receiver circuits and methods minimally affected by voltage, process, and temperature variations.
It is another object of the present invention to provide receiver circuits and methods for optimally compensating a received signal by using a variable adaptive algorithm.
It is yet another object of the present invention to provide adaptation circuits and methods for optimally compensating a received signal and minimizing errors.
Briefly, the present invention discloses methods and circuits utilizing a two stage adaptation algorithm to determine the optimal code to minimize errors. In the first stage, a coarse tuning algorithm is used to choose a range of codes based on the amplitude of the received signal. The chosen codes will be used as reference points in the second stage. In the second stage, a fine tuning algorithm is used to select a code in the range of reference codes determined in stage one. The fine tuning algorithm looks to the status of the data lock signal generated by the clock recovery circuit. If the data lock signal does not indicate a lock, the fine tuning algorithm cycles through the range of reference codes. If the data lock signal indicates a lock, then that particular code is continued to be used for the equalizer.
An advantage of the present invention is that it provides reliable receiver circuits and methods minimally affected by voltage, process, and temperature variations.
Another advantage of the present invention is that it provides receiver circuits and methods for optimally compensating a received signal by using a variable adaptive algorithm.
Yet another advantage of the present invention is that it provides adaptation circuits and methods for optimally compensating a received signal and minimizing errors.
REFERENCES:
patent: 4327412 (1982-04-01), Timmons
patent: 5274512 (1993-12-01), Tanaka et al.
patent: 5517213 (1996-05-01), Bhatt et al.
patent: 6370190 (2002-04-01), Young et al.
patent: 6389062 (2002-05-01), Wu
Chen Xi
Lenguyen Bao
Wu Wen-Chung (Stewart)
Ahn Sam K
Altima Communications, Inc.
Chin Stephen
Squire Sanders & Dempsey L.L.P.
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