Excavating
Patent
1987-07-30
1989-04-11
Fleming, Michael R.
Excavating
371 25, G01R 3128
Patent
active
048212717
ABSTRACT:
A functional-redundancy checking logic for checking identical chips whose outputs are time-variant programmable. Window logic (40, 60) on each chip creates a window associated with each programmed transition, set pulse (14) and reset pulse (15). For the set pulse (14), on the rising edge (42) of the window, an error flip-flop (50) is set. The flip-flop is merely set at this time; an error is not flagged. The window remains open for a fixed time period. During the time period that the window is open, if the output pin (24) is ever correctly asserted, then the flip-flop (50) is reset, thus clearing the error flag. However, if the pin (24) always remains incorrectly asserted, indicating an error, then the error flip-flop (50) remains set. When the window closes on the falling edge (46) of the window pulse, an error report pulse is created via the AND (52). The value on the flip-flop (50) at this time is reported as an error (54). An identical circuit checks the programmable reset pulse ( 15).
REFERENCES:
patent: 4176258 (1979-11-01), Jackson
patent: 4309768 (1982-01-01), Ault
patent: 4583041 (1986-04-01), Kimura
patent: 4710930 (1987-12-01), Hatayama
patent: 4739504 (1988-04-01), Leslie
patent: 4739505 (1988-04-01), Leslie
patent: 4739506 (1988-04-01), Leslie
Kini M. Vittal
Myers Mark S.
Shenoy Sunil
Fleming Michael R.
Intel Corporation
Lamb Owen L.
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