Methods and circuit for implementing and arbitrary graph on a po

Details Methods and circuit for implementing and arbitrary graph on a po Methods and circuit for implementing and arbitrary graph on a po

1992-05-26

1993-10-26

Lee, Thomas C.

Boots, shoes, and leggings

3642281, 3642283, 3642294, 3642319, 3642531, 3642548, 3642598, 364DIG1, G06F 1580

Patent

active

052573958

ABSTRACT:
A single instruction multiple datastream (SIMD) polymorphic mesh network array processing system is modified by the inclusion of a single instruction multiple address (SIMA) circuit including a content addressable packet buffer memory to enable processing of an algorithm representing an arbitrary graph. Packets of address information and related data information associated with each independently addressable processing element forming the polymorphic mesh network array are transferred between the processing elements in accordance with one of a first-available method, a force transfer method, or a buffer sensitive method.

REFERENCES:
patent: 3320594 (1967-05-01), Davies
patent: 3537074 (1970-10-01), Stokes et al.
patent: 3675215 (1972-07-01), Arnold et al.
patent: 3764996 (1973-10-01), Ross
patent: 3840863 (1974-10-01), Fuqua et al.
patent: 3958222 (1976-05-01), Messina et al.
patent: 3970993 (1976-07-01), Finnila
patent: 4101960 (1978-07-01), Stokes et al.
patent: 4344134 (1982-08-01), Barnes
patent: 4365292 (1982-12-01), Barnes et al.
patent: 4412303 (1983-10-01), Barnes et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4498134 (1985-02-01), Hansen et al.
patent: 4507748 (1985-03-01), Cotton
patent: 4523273 (1985-06-01), Adams et al.
patent: 4546428 (1985-10-01), Morton
patent: 4574348 (1986-03-01), Scallon
patent: 4580215 (1986-04-01), Morton
patent: 4598400 (1986-07-01), Hillis
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4739474 (1988-04-01), Holsztynski
patent: 4783738 (1988-11-01), Li et al.
patent: 4805093 (1989-02-01), Ward
patent: 4809346 (1989-02-01), Shu
patent: 4809347 (1989-02-01), Nash et al.
patent: 4850027 (1989-07-01), Kimmel
patent: 4870568 (1989-09-01), Kahle et al.
patent: 4873626 (1989-10-01), Gifford
patent: 4901360 (1990-02-01), Shu et al.
patent: 5038386 (1991-08-01), Li
patent: 5058001 (1991-10-01), Li
patent: 5081575 (1992-01-01), Hiller et al.
A. Azizienis et al, "A Fault-Tolerant Parallel Computer System for Signal Processing", 4th FTCS, 1974.
Chen et al, IBM Technical Disclosure Bulletin, vol. 22, No. 6, p. 2491, Nov. 1979.

Affiliated with

Also associated with

Rating

Methods and circuit for implementing and arbitrary graph on a po does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and circuit for implementing and arbitrary graph on a po, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and circuit for implementing and arbitrary graph on a po will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-966258