Methods and arrangements to model an asynchronous interface

Details Methods and arrangements to model an asynchronous interface Methods and arrangements to model an asynchronous interface

2011-08-09

2011-08-09

Ngo, Ricky (Department: 2464)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C368S117000, C710S058000, C713S400000

Reexamination Certificate

active

07995619

ABSTRACT:
Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may than alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, chances to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

REFERENCES:
patent: 5553276 (1996-09-01), Dean
patent: 5598113 (1997-01-01), Jex et al.
patent: 5901116 (1999-05-01), Quine
patent: 6876678 (2005-04-01), Chow et al.
patent: 2002/0013875 (2002-01-01), Dreps et al.
patent: 2002/0144189 (2002-10-01), Chen
patent: 2003/0046596 (2003-03-01), Floyd et al.
patent: 2003/0101015 (2003-05-01), Douskey et al.
patent: 2005/0069068 (2005-03-01), Gundurao et al.
patent: 2005/0122810 (2005-06-01), Lee
patent: 2005/0251773 (2005-11-01), Bair et al.
patent: 2006/0233291 (2006-10-01), Garlepp et al.
patent: 2008/0201599 (2008-08-01), Ferraiolo et al.
Hoke, J.M., et al., “Self-timed Interface of the Input/Output Subsystem of the IBM eServer z900,” IBM J. Res & Dev., vol. 46, No. 4/5, Jul./Sep. 2002, pp. 447-460.
Hoke, J.M., et al., “Self-timed Interface for S/390 I/O Subsystem Interconnection,” IBM J. Res & Dev., vol. 43, No. 5/6, Sep./Nov. 1999, pp. 829-846.
Wang, David T., “A Brief Overview of High Frequency Processor-System Interconnects,” http://www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT01130318314&mode=print, Updated: Jan. 13, 2003, pp. 1-8.
Greenstreet, Mark R., “Implementing a STARI Chip,” Vancouver, B.C., V6T 1Z4 Canada, pp.-6, 1995.

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