Methods and arrangements to adjust a duty cycle

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S172000, C327S173000, C327S174000

Reexamination Certificate

active

11377507

ABSTRACT:
Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

REFERENCES:
patent: 6040726 (2000-03-01), Martin
patent: 6940328 (2005-09-01), Lin
patent: 7019574 (2006-03-01), Schrodinger
patent: 2005/0007168 (2005-01-01), Park et al.
Jang, Y.C., et al., “CMOS Digital Duty Cycle Correction Circuit for Multi-Phase Clock,” Electronics Letters, Sep. 2004, pp. 1383-1384.
Wang, Yi-Ming, et al., “An All-Digital 50% Duty-Cycle Corrector,” ISCAS, vol. 2, 2004, pp. II-925-928.
Tajalli, A., et al., “A Duty Cycle Control Circuit for High Speed Applications,” ISCAS, vol. 1, 2004, pp. I-781-784.
Cheng, Kuo-Hsing, et al., “A Phase-Locked Pulse Width Control loop with Programmable Duty Cycle,” Advanced System Integrated Circuits 2004, Proc. of 2004 IEEE Asia-Pacific, pp. 84-87.
Young, I. A., et al., A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors, IEEE JSSC., vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Karthikeyan, S., “Clock Duty Cycle Adjuster Circiut for Switched Capacitor Circuits,” Electronics Letters, vol. 38, No. 18, Aug. 29, 2002, pp. 1008-1009.
Nakamura, K., et al., “A CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending,” 2000 Symposium on VLSI Circuits Digest of Tech. Papers, pp. 48-49.
Ogawa, T., et al., “50% Duty-Cycle Correction Circuit for PLL Output,” IEEE ISCAS, May 26-29, 2002, pp. IV-21-24.
Chow, Hwang-Cherng, “Duty Cycle Control Circuit and Applications to Frequency Dividers,” Proc. of ICECS Sep. 1999, pp. 1619-1622.
Simon, Tam, et al., “Clock Generation and Distribution for the First IA-64 Microprocessor,” IEEE JSSC., vol. 35, No. 11, Nov. 2000, pp. 1545-1552.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods and arrangements to adjust a duty cycle does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and arrangements to adjust a duty cycle, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and arrangements to adjust a duty cycle will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3849344

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.