Methods and arrangements for link power reduction

Details Methods and arrangements for link power reduction Methods and arrangements for link power reduction

2007-11-15

2008-12-30

Tran, Khanh C (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

07471755

ABSTRACT:
Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.

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