Methods and apparatuses for memory array leakage reduction...

Details Methods and apparatuses for memory array leakage reduction... Methods and apparatuses for memory array leakage reduction...

2006-12-12

2006-12-12

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

Data preservation

C365S226000

Reexamination Certificate

active

07149142

ABSTRACT:
Various methods, apparatuses, and systems are described in which a volatile memory that includes a plurality of volatile memory cells as well as a voltage limiting component and a current limiting component. Power consumption in a standby mode is controlled. The voltage limiting component and the current limiting component couple between the volatile memory cells and the ground voltage potential. One or more rows of memory cells in the memory array are isolated from the ground voltage potential to control power consumption in the standby mode by having the current limiting component stop passing current in the standby mode. A floating ground voltage potential sensed by each memory cell when in the standby mode is controlled by configuring the voltage limiting component to conduct when the floating ground voltage potential is larger than a threshold voltage of the voltage limiting component in order to reduce leakage current but reliably maintain the stored contents of the volatile memory cell. The floating ground voltage potential is internally raised higher than a voltage biasing the bulk of the transistors in the volatile memory cells by coupling the floating ground voltage potential to the voltage limiting component.

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