Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2003-12-17
2008-11-04
Vu, Tuan Anh (Department: 2193)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
Reexamination Certificate
active
07448031
ABSTRACT:
Methods and apparatus to compile a software program to manage parallel μ caches are disclosed. In an example method, a compiler attempts to schedule a software program such that load instructions in a first set of load instructions has a first predetermine latency greater than the latency of the first cache. The compiler also marks a second set of load instructions with a latency less than the first predetermined latency to access the first cache. The compiler attempts to schedule the software program such that the load instruction in a third set have at least a second predetermined latency greater than the latency of the second cache. The compiler identifies a fourth set of load instructions in the scheduled software program having less than the second predetermined latency and marks the fourth set of load instructions to access the second cache.
REFERENCES:
patent: 5357618 (1994-10-01), Mirza et al.
patent: 5499354 (1996-03-01), Aschoff et al.
patent: 5586296 (1996-12-01), Bernstein et al.
patent: 5625793 (1997-04-01), Mirza
patent: 5751946 (1998-05-01), Afsar et al.
patent: 5860078 (1999-01-01), Emmot
patent: 6052775 (2000-04-01), Panwar et al.
patent: 6134710 (2000-10-01), Levine et al.
patent: 6202204 (2001-03-01), Wu et al.
patent: 6226722 (2001-05-01), Shippy et al.
patent: 6230317 (2001-05-01), Wu
patent: 6332214 (2001-12-01), Wu
patent: 6446145 (2002-09-01), Har et al.
patent: 6516462 (2003-02-01), Okunev et al.
patent: 6564299 (2003-05-01), Auracher
patent: 6571385 (2003-05-01), Muthukumar et al.
patent: 6625725 (2003-09-01), Wu et al.
patent: 6629314 (2003-09-01), Wu
patent: 6668372 (2003-12-01), Wu
patent: 6684299 (2004-01-01), Hetherington et al.
patent: 6698015 (2004-02-01), Moberg et al.
patent: 6836841 (2004-12-01), Wu et al.
patent: 6848100 (2005-01-01), Wu et al.
patent: 6959435 (2005-10-01), Ju et al.
patent: 6961930 (2005-11-01), Waldspurger et al.
patent: 6964043 (2005-11-01), Wu et al.
patent: 7039909 (2006-05-01), Wu et al.
patent: 2003/0126591 (2003-07-01), Wu et al.
patent: 2003/0204666 (2003-10-01), Wu
patent: 2003/0204840 (2003-10-01), Wu
patent: 2005/0149915 (2005-07-01), Wu
patent: 2005/0210197 (2005-09-01), Rakvic et al.
patent: 2005/0240896 (2005-10-01), Wu et al.
Rotenberg et al., ‘Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching’, copyright 1996, Proceedings of the 29th Annual International Symposium on Microarchitecture, Dec. 1996, pp. 1-12.
“Intel Itanium 2 Processor.” http://www.intel.com/products/server/processors/server/itanium2/. Printed on Aug. 9, 2002.
“Itanium.” http://searchhp.techtarget.com/sDefinition/0,,sid6—gci214552,00.html. Printed on Aug. 9, 2002.
“EPIC.” http://searchhp.techtarget.com/sDefinition/0,,sid6—gci214560,00.html. Printed on Aug. 9, 2002.
C.-H. Chi et al. “Improving Cache Performance By Selective Cache Bypass.” Proceedings of the Twenty-Second Annual Hawaii International Conference On System Sciences, 1989. vol. I: Architecture Track, 1989. pp. 277-285. 1989.
J. Crawford. “Introducing The Itanium Processors.” IEEE Micro,Sep./Oct. 2000 (vol. 20, No. 5). pp. 9-11. 2000.
J. Bharadwaj et al. “Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs.” Micro 32, Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture. pp. 262-271. 2000.
B. Fields et al. “Slack: Maximizing Performance Under Technological Constraints.” Proceedings of The 29th International Symposium on Computer Architecture (ISCA '02), 2002.
B. Fields et al. “Focusing Processor Policies via Critical-Path Prediction.” The 28th International Symposium on Computer Architecture (ISCA '01), 2001.
B. Fisk et al. “The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency.” IEEE International Conference On Computer Design. Oct. 1999.
R. Johnson et al. “Dependence-Based Program Analysis.” Dependence-Based Program Analysis. ACM SIGPLAN'93 Conference on Programming Language Design and Implementation. pp. 78-89. 1993.
T. L. Johnson et al. “Run-Time Cache Bypassing.” IEEE Transactions on Computers, vol. 48, No. 12, Dec. 1999, pp. 1338-1354. 1999.
N. Kurd et al. “A Multigigahertz clocking scheme for the Pentium 4 microprocessor”, JSSC, vol. 36, Nov. 2001, pp. 1647-1653. 2001.
A. Lebeck et al. “Cache Profiling and the SPEC Benchmarks: A Case Study.” IEEE Computer 27(10). pp. 15-26. 1994.
H.-H. S. Lee et al. “Region-Based Caching: An Energy-Delay Efficient Memory Architecture For Embedded Processors.” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2000. pp. 120-127. 2000.
P. Livadas et al. “Program Dependence Analysis.” Proceedings of International Conference On Software Maintenance. pp. 356-365. 1992.
S. Mahlke et al. “Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution.” Transactions on Computer Systems, vol. 11, No. 4, Nov. 1993, pp. 376-408. 1993.
R. Rakvic et al. “Non-vital Loads.” Proceedings of the Eighth International Symposium on High-Performance Computer Architecture. 2002.
J. Rives et al. “Reducing Conflicts In Direct-Mapped Caches With A Temporality-Based Design.” Proceedings of the 1996 International Conference on Parallel Processing, vol. I. pp. 154-163. 1996.
M. Schlansker et al. “EPIC: Explicitly Parallel Instruction Computing.” IEEE Computer, Feb. 2000. pp. 37-45. 2000.
H. Sharangpani et al. “Itanium Processor Microarchitecture.” IEEE Micro , vol. 20 Issue: 5 , Sep.-Oct. 2000. pp. 24-43. 2000.
S. Srinivasan et al. “Locality vs. Criticality.” Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001.
A. Stoutchinin et al. “Speculative Prefetching of Induction Pointers.” Compiler Construction, 10th International Conference. 2001.
E. Tam et al. “Active Management Of Data Caches By Exploiting Reuse Information.” IEEE Transactions on Computers 48(11). pp. 1244-1259. 1999.
J. Lo. et al. “Improving Balanced Scheduling With Compiler Optimizations That Increase Instruction-Level Parallelism.” Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI). Jun. 1995.
International Search Report, International Bureau, Oct. 10, 2004, 3 pages.
Johnson et al., “Run-Time Adaptive Cahse Hierarchy Via Reference Analysis”, Coference Proceedigns Article, Jun. 2, 1997, pp. 315-326.
Johnson et al., “Run-Time Cache Bypassing”, IEEE Transactions on Computers, IEEE Inc., New York, vol. 48, No. 12, Dec. 1999, pp. 1338-1354.
Ortega et al., “Cost-Effective Compiler Directed Memory Prefetching and Bypassing”, Conference Proceedings Article, Sep. 22, 2002, pp. 189-198.
Zalamea et al., “Two-Level Hierarchical Register File Organization for VLIW Processors”, Micro-33. Proceedings of the 33rd, Annual ACM/IEEE International Symposium on Microarchitecture, Monterey, California, Dec. 10-13, 2000, pp. 137-146.
Choi Y., Knies A., Vedaraman G., Williamson J.,Design and Experience: Using the Intel Itanium 2 Processor Performance Monitoring Unit to Implement Feedback Optimizations, 2ndWorkshop on EPIC Architectures and Compiler Technology, pp. 1-11, XP002326247, pp. 1-3 (Nov. 18, 2002).
Chilimbi, T.M.,Efficient Representations and Abstractions for Quantifying and Exploiting Data Reference Locality, ACM SIGPlan 2001 Conference on Programming Language Design and Implementation, pp. 1-12, XP002326248, pp. 4-5; Fig. 4 (Jun. 2001).
Inagaki, T., Onodera, T., Komatsu, H., Nakatani, T.,Stride Prefetching by Dynamically Inspecting Object, Proceedings of the ACM SIGPlan 2003 Conference on Programming Language Design and Implementation, pp. 269-277, XP002326249, p. 274 (Jun. 9, 2003).
Chilimbi, T.M., et al.,Using Generational Garbage Collection to Im
Hanley Flight & Zimmerman LLC
Intel Corporation
Vu Tuan Anh
LandOfFree
Methods and apparatus to compile a software program to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus to compile a software program to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus to compile a software program to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4040456