Methods and apparatus to avoid dynamic micro-architectural...

Details Methods and apparatus to avoid dynamic micro-architectural... Methods and apparatus to avoid dynamic micro-architectural...

2006-08-29

2006-08-29

Zhen, Wei (Department: 2191)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S151000, C717S159000

Reexamination Certificate

active

07100157

ABSTRACT:
Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor are disclosed. In an example, a compiler inserts decision code into the object code to thereby cause the in-order processor to operate like an out of order processor to operate with respect to at least some memory access instructions. The decision code determines at run time of the object code whether a load instruction is a likely cache hit. Based on that determination, the decision code causes the in-order processor to execute a use instruction at a first time if the load instruction is a likely cache hit, and to execute a copy of the use instruction at a second, later time if the load instruction is not a likely cache hit.

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