Methods and apparatus to analyze processor systems

Data processing: software development – installation – and managem – Software program development tool – Testing or debugging

Reexamination Certificate

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C717S126000, C717S127000, C717S128000, C717S131000, C717S151000, C717S158000, C714S038110

Reexamination Certificate

active

07739662

ABSTRACT:
Methods and apparatus are disclosed to analyze processor system. An example method to analyze execution of a multi-threaded program on a processor system includes generating a first program trace associated with the execution of a first thread, generating a first list of execution frequencies associated with the first program trace, generating a second program trace associated with the execution of a second thread, generating a second list of execution frequencies associated with the second trace, generating a first set of one or more vectors for the first list of execution frequencies, generating a second set of one or more vectors for the second list of execution frequencies, and analyzing the one or more vectors to identify one or more program phases.

REFERENCES:
patent: 5606685 (1997-02-01), Frandeen
patent: 5850632 (1998-12-01), Robertson
patent: 6055650 (2000-04-01), Christie
patent: 6237065 (2001-05-01), Banerjia et al.
patent: 6314530 (2001-11-01), Mann
patent: 6415359 (2002-07-01), Kimura et al.
patent: 6571318 (2003-05-01), Sander et al.
patent: 6622168 (2003-09-01), Datta
patent: 6751707 (2004-06-01), Magoshi
patent: 6752335 (2004-06-01), Levia
patent: 2001/0042172 (2001-11-01), Duesterwald et al.
patent: 2001/0052064 (2001-12-01), Chaudhry et al.
patent: 2002/0152361 (2002-10-01), Dean et al.
patent: 2003/0105942 (2003-06-01), Damron et al.
patent: 2003/0140203 (2003-07-01), Jordan et al.
patent: 2004/0103408 (2004-05-01), Chilimbi et al.
patent: 2004/0111708 (2004-06-01), Calder et al.
patent: 2004/0128658 (2004-07-01), Lueh et al.
patent: 2004/0154011 (2004-08-01), Wang et al.
patent: 2004/0215668 (2004-10-01), Sun
patent: 2004/0216097 (2004-10-01), Sun
Wu, et al. “From Trace Generation to Visualization: A Performance Framework for Distributed Parallel Systems”, 2000, IEEE, p. 1-18.
Kaplan, S. “Collecting Whole-System Reference Traces of Multiprogrammed and Multithreaded Workloads”, 2004, ACM, p. 228-237.
U.S. Appl. No. 10/424,356, filed Apr. 28, 2003, Sun.
U.S. Appl. No. 10/833,762, filed Apr. 28, 2004, Sun.
Hazelwood et al.,Code Cache Management Schemes for Dynamic Optimizers, Proceedings of the Sixth Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT'02), 2002, 9 pages.
Doug Joseph et al., “Prefetching using Markov Predictors”, 1997 Proceedings of the International Symposium on Computer Architecture (ISCA'97), Jun. 1997, Denver Colorado, p. 1-13.
Trishul M. Chilimbi et al., “Dynamic Hot Data Stream Prefetching for General-Purpose Programs”, PLDI-2002, May 2002, p. 1-12.
Mingqiu Sun et al., “Entropy-based Characterization of Program Phase Behaviors”, Feb. 2004, Madrid Spain, CTG-MTL, Intel Labs, p. 1-8.
S. Dhodapkar et al., “Comparing Program Phase Detection Techniques”, Micro-2003, 2003, p. 1-12.
V. Bala et al., “Dynamo: A transparent dynamic optimization system”, PLDI'2000, Jun. 2000, p. 1-13.
B. Balasubramonian et al., “Memory Hierarchy Reconfiguration for Energy and Performance in General Purpose Architectures”, Micro-2000, Dec. 2000, p. 1-14.
J. E. Smith et al., “Dynamic Microarchitecture Adaptation via Co-designed Virtual Machines”, ISSCC-2002, Feb. 2002, p. 1-4.
M. Huang et al., “Positional Adaptation of Processors: Application to Energy Reduction”, ISCA-2003, Jun. 2003, p. 1-13.
T. Sherwood et al., “Phase Tracking and Prediction”, ISCA-2003, Jun. 2003, p. 1-13.
T. Sherwood et al., “Automatically Characterizing Large Scale Program Behavior”, ASPLOS-2002, Oct. 2002, p. 1-14.
C.E. Shannon, “A Mathematical Theory of Communication”, Bell Syst. Tech. J., 27, 379-423, 623-656. Jul. and Oct. 1948.
Standard Performance Evaluation Corperation(SPEC) JBB2000 [online]. SPEC [retrieved on Apr. 17, 2006: Retrieved from the Internet: <URL: http://web.archive.org/web/20041011042918/www.spec.org/jbb2000>, 2 pages.
Standard Performance Evaluation Corperation(SPEC) JBB2000 [online]. SPECjAppServer [retrieved on Apr. 17, 2006]: Retrieved from the Internet: <URL: http://www.web.archive.org/web/20040413033403/www.spec.org/jAppSer>, 2 pages.
Dinero IV Trace-Driven Uniprocessor Cache Simulator: [retrieved on Apr. 17, 2006]: Retrieved from the Internet: <URL: http://www.web.archive.org/web/20040603081702/www.cs.wisc.edu>, 2 pages, Edler, et al.
Annavaram et al.,The Fuzzy Correlation between Code and Performance Predictability, Proceeding of the 37thInternational Symposium on Microarchitecture, 2004, 12 pages.
Peggy Irelan,Evaluating Instrucions Retired Events on Intel® Processors with Hyper-Threading Technology, [retrieved on Dec. 9, 2005]: Retrieved from the Internet: URL: http://www.intel.com.cd/ids/developer/asmo-na/eng/20468.htm, 11 pages.
Sherwood et al.,Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications, Department of Computer Science and Engineering, University of California, San Diego, in proceedings of the International Conference on Parallel Architecture and Compilation Techniques (PACT), Sep. 2001, 12 pages.
Patil et al.,Pinpointing Representative Portions of Large Intel® Itanium® Architecture Programs with Dynamic Instrumentation, Proceedings of the 37thAnnual IEEE/ACM International Symposium on Microarchitecture, 2004, 12 pages.
Ashutosh S. Dhodapkar et al., “Managing Multi-Configuration Hardware via Dynamic Working Set Analysis”, May 2002, 12 pages., retrieved from http://www.cae.wisc.edu/˜dhodapka/isca02.pdf.
Davies et al., iPart: An Automated Phase Analysis and Recognition Tool, Microprocessor Research Labs-Intel Corporation-SC12-303, Santa Clara, California, 12 pages, 2004.
Ekman et al., Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison, Department of Computer Science and Engineering Chalmers University of Technology, Goteborg, Sweden, 11 pages, Mar. 20-22, 2005.
Sherwood et al., Phase Tracking and Prediction, Department of Computer Science and Engineering University of California, San Diego, 12 pages, In Proceedings of the 30th International Symposium on Computer Architecture (ISCA), Jun. 2003.

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