Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1994-07-19
1996-07-02
Wieder, Kenneth A.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324754, G01R 3102
Patent
active
055326129
ABSTRACT:
Methods and specially adapted reusable test carriers provide for burn-in test of semiconductor integrated circuit devices and economical production of known good dice (KGD). Methods for temporary flip-chip mounting of IC wafers or dice use a hierarchy of solder melting points in combination with improved reusable carrier substrates. IC chip wafers having high-melting-temperature flip-chip terminals are coated with a predetermined volume of a sacrificial solder having a significantly lower melting temperature. A reusable temporary carrier is provided, in a range of sizes adapted for a wafer, small numbers of IC dice, or an individual die, For full-wafer burn-in, the reusable carrier has edge connector terminals. For testing individual dice or a small number of dice, the reusable carrier has conductive elements in a pattern matching each IC dies terminal pattern. The same or opposite side of the reusable carrier has pins or ball-grid array matching a conventional burn-in socket. A preferred reusable carrier consists of separable parts: a substrate customized to carry specific dice for burn-in, and a "universal" carrier package adapted to fit standard test sockets. After burn-in testing, the known good dice are removed by a low-temperature reflow, and attached to permanent substrates by conventional high-temperature reflow. The test carriers are re-usable after cleaning. A carrier structure similar to the preferred separable structure is specially adapted for testing and/or permanent packaging of IC chips which utilize wire-bond connections.
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Khosravi Kourosh Cyrus
Touw Theodore R.
Wieder Kenneth A.
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