Methods and apparatus for synthesizing a clock signal

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S158000, C327S116000, C327S113000

Reexamination Certificate

active

06909311

ABSTRACT:
One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay signal having a first period and a first phase, and at least some falling edges of the timing signal are based on edges of a second delay signal having a second period that is substantially the same as the first period, and a second phase that is different from the first phase. Another embodiment of the invention is directed to a programmable clock synthesizer comprising an edge-triggered circuit that receives a rising edge delay signal and a falling edge delay signal, wherein the edge-triggered circuit is adapted to generate a synthesized clock signal having rising edges triggered in response to edges of the rising edge delay signal and falling edges triggered in response to edges of the falling edge delay signal.

REFERENCES:
patent: 6031401 (2000-02-01), Dasgupta
patent: 6690219 (2004-02-01), Chuang
Paul C. Davis, Karl R. Gardner and Alan M. Gordon, “A Fully Integrated Timing Generator for the PICTUREPHONE Video-Telephone Camera,” IEEE J. Solid-State Circuits, vol. 4, No. 5, pp. 259-263, Oct. 1969, USA.

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