Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Reexamination Certificate
1997-03-10
2001-08-14
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
C375S219000
Reexamination Certificate
active
06275549
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to methods and apparatus for synchronizing a clock between first and second logic blocks connected by an asynchronous bus wherein the second logic block includes a clock signal generator responsive to an input synchronizing signal to generate a clock signal synchronized with the synchronizing signal.
The invention has application in a variety of fields but is particularly suited to applications in which the logic blocks are incorporated in a PC linked to an external telephone system, for example for providing digital voice links to the telephone system.
BACKGROUND OF THE INVENTION
The basic operation of digital voice links within a telephone system relies on parts of the telephone network operating with a common clock reference signal (typically based around 8 kHz). For example the local telephone exchanges at each end of a conventional telephone call will both use the same clock reference signal to ensure that voice signals converted from analogue to digital form at one exchange are converted back from digital to analogue form at the same rate. Therefore there is no over-run or under-run of digitized voice signals within the digital part of the phone network.
With the advent of digital services such as ISDN it is practical and desirable for the digital phone system to be extended to the user, rather than converting voice signals from analogue to digital form at the first telephone exchange.
By connecting personal computers to the digital telephone network users can make use of the network directly for voice, data and video conferencing. However for correct operation the timing reference signals must still be propagated within the PC to any devices generating or processing data for the digital telephone network. This invention provides inter alia a novel way of maintaining such timing within a PC.
Typically the communications within a personal computer for video conferencing is broken into two modules or logic blocks plugged into the ISA bus (or other standard PC bus). An ISDN network interface on a first card (defining a first logic block) recovers the serial bit stream from the public network. This bit stream then crosses a synchronous interface provided by a ribbon cable (i.e. not via the personal computer asynchronous bus) to a second card (defining a second logic block) that processes the received bit stream for display and compresses the camera input to be passed back along the synchronous interface to the ISDN link.
The synchronous link undertakes two basic functions:
1. Passing the transmit and receive data between the two cards (in this case about 16 Kbytes/sec in each direction).
2. Propagating the timing reference from the public phone network, via the ISDN interface to synchronize the operation of the video codec.
The main problem with this known technique is the requirement for an additional cable to provide a synchronous link between the two cards. This leads to additional mechanical complexity and additional cost.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, we provide a method of synchronizing a clock between first and second logic blocks connected via an asynchronous bus wherein the second logic block includes a clock signal generator responsive to an input synchronizing signal to generate a clock signal synchronized with the synchronizing signal the method comprising transferring data in blocks from the first logic block to the second logic block across the asynchronous bus; and utilizing the receipt of a data block by the second logic block to generate the synchronizing signal.
In accordance with a second aspect of the present invention, we provide apparatus for synchronizing a clock between first and second logic blocks connected by an asynchronous bus wherein the second logic block includes a clock signal generator responsive to an input synchronizing signal to generate a clock signal synchronized with the synchronizing signal the apparatus comprising a first data transfer controller on the first logic block for controlling transfer of data in blocks across the asynchronous bus; and a data block receipt detector on the second logic block for detecting the receipt of a data block and for generating a synchronizing signal related to the receipt of a data block, the synchronizing signal being fed to the clock signal generator on the second logic block.
We have devised a method and apparatus which enables a clock on the second logic block to be synchronized with a clock on the first logic block by utilizing data transfers across the asynchronous bus and thus without the need for a separate ribbon cable.
The synchronizing signal can be generated, inter alia, by the leading or trailing edge of the block of data.
Typically the method further comprises storing data in a memory, for example a FIFO, on the second logic block and reading out data from the memory using the clock signal generated by the clock signal generator of the second logic block. Thus data which is intended for the second logic block can additionally be used for clock synchronization purposes. In some cases, however, dummy data could be transmitted across the asynchronous bus and then discarded once it has been used to synchronize the clock signal generator.
So far, the invention has been described in connection with the transfer of data from the first logic block to the second logic block. In many cases, the method further comprises transferring data from the second logic block to the first logic block using a clock signal generated by the clock signal generator. In this way, two-way communication can be set up which is particularly suitable when the method and apparatus are to be utilized in a telephone environment, either voice or video.
Typically, a second data transfer controller would be provided on either the first or second logic block to enable data to be transferred from the second logic block to the first logic block. Where the second data transfer controller is located on the second logic block then it can be made responsive to the clock signal generated by the clock signal generator.
Conveniently, the first and/or second data transfer controllers comprise direct memory access (DMA) controllers.
In some cases, the first logic block could include a clock signal generator with which the second logic block is to be synchronized. Typically, however, the first logic block will be connected to an external clock signal source, the method causing the clock signal generator on the second logic block to be synchronized with the external clock signal. For example, in the case of a telephone application, the first logic block will be connected to a telephone network to receive data from the network which will be transmitted to the first logic block in accordance with the network clock.
The clock signal generator can take a variety of forms but preferably comprises a phase locked loop (PLL). The PLL is responsive to incoming synchronization signals to generate a clock signal related to the frequency of the synchronizing signals.
In general, it is not essential for every data block transfer to be utilized to generate a synchronizing signal and for this to be periodic but sufficiently frequent to maintain the frequency generated by the clock signal generator at the desired frequency.
In some cases, particularly where the logic blocks are defined by respective PC cards, it is not possible to transfer data directly from one card to the other via the asynchronous bus. In these cases, data is transferred via the asynchronous bus and a host memory (for example of a host PC).
REFERENCES:
patent: 4494211 (1985-01-01), Schwartz
patent: 4856030 (1989-08-01), Batzer et al.
patent: 5022050 (1991-06-01), Tanaka
patent: 5062124 (1991-10-01), Hayashi et al.
patent: 5111451 (1992-05-01), Piasecki et al.
patent: 5319678 (1994-06-01), Ho et al.
patent: 5512938 (1996-04-01), Ohno
patent: 5790608 (1998-08-01), Benayoun et al.
patent: 0 530 846 A2 (1993-03-01), None
patent: 2 182 828 (1987-05-01), None
U.K. Search Report dated Jun. 2, 1
Claridge Philip Geoffrey
Greatwood Duncan McDougall
Madge Networks Limited
Sughrue Mion Zinn Macpeak & Seas, PLLC
Tse Young T.
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