Methods and apparatus for scheduling ATM cells

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

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370468, H04L 1256

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active

059403977

ABSTRACT:
A method for scheduling and transmitting data cells includes providing a plurality of scheduling lists associated with a plurality of priorities that include a plurality of fields therein, assigning a virtual circuits to the scheduling lists by placing identifiers in some of the fields, sequentially indexing through the lists/fields, and transmitting specific data cells depending upon which identifier is indexed first given the priority of the scheduling lists. The method can include scheduling a next transmission time for a virtual circuit by determining an ideal time based a data rate associated with the virtual circuit, and placing an identifier in a field corresponding to the ideal time or the next available field within the scheduling list that the virtual circuit is assigned to. A scheduler includes a processor, an interface module and a buffer. The processor is configured to generate scheduling lists, assign virtual circuits to the scheduling lists, and index through the fields within the scheduling lists. The interface module allows the scheduler to access an external memory for storing the scheduling lists generated by the processor. The buffer is configured to transmit a data cell that is associated with an indexed virtual circuit over the network.

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Unknown, "155 Mbps ATM SAR Controller for PCI-Based Networking Applications", Jan. 1996, pp. 1-26, Integrated Device Tech., Inc., Santa Clara, CA.

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