Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1998-12-18
2000-08-08
Treat, William M.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 22, 712 24, 712209, 712212, G06F 1580
Patent
active
06101592&
ABSTRACT:
A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
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Barry Edwin F.
Larsen Larry D.
Pechanek Gerald G.
Revilla Juan Guillermo
Billions of Operations Per Second, Inc.
Treat William M.
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