Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2001-09-28
2003-04-29
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S010000, C712S016000, C712S024000
Reexamination Certificate
active
06557094
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to improvements in array and indirect Very Long Instruction Word (iVLIW) processing, and more particularly to a scalable instruction set architecture which is hierarchically defined.
BACKGROUND OF THE INVENTION
The Instruction Set Architecture (ISA) of a processor defines its operational characteristics. Given the development investment in tools and application code for the processor, the ISA typically represents a fixed quantity with minimal room for growth. It is possible to develop supersets of an instruction set architecture, but even this is many times difficult given that the overall fixed core ISA is usually defined without scalability, i.e., planned growth, in mind. In addition, it is a difficult problem to develop a single ISA for a family of array processors in order to amortize development expenses across a family of products, encompassing a range of 16-bit, 32-bit, and larger instruction set formats. Thus, it has been recognized that it will be highly advantageous to have a hierarchical instruction set as discussed further below.
SUMMARY OF THE INVENTION
A manifold array (ManArray) architecture in accordance with the present invention solves the problem of instruction set scalability by defining a hierarchical instruction set which includes pluggable instruction set capability and support for array processors. The hierarchical instruction set allows application specific processors to be developed which contain new instructions that provide optimized capabilities for specific applications. These capabilities can result in higher performance, improved code density, and new functionality, such as support for low power features. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements.
One specific aspect addressed by this invention is a unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions. Advantageous characteristics of the ManArray ISA are:
Hierarchical ISA for future growth
Support for uniprocessors
Support for single PE designs as well as M×N array processors
Dynamic application specific pluggable instructions
Improved code density
Designed for standard bus and memory sizes, in multiples of 16-bits:
16-bit ISA
32-bit ISA
48-bit ISA
64-bit ISA
and so on.
These and other advantages of the present invention will be apparent from the drawings and the Detailed Description which follows.
REFERENCES:
patent: 6101592 (2000-08-01), Pechanek et al.
patent: 6321322 (2001-11-01), Pechanek et al.
Barry Edwin F.
Larsen Larry D.
Pechanek Gerald G.
Revilla Juan Guillermo
Bops, Inc.
Priest & Goldstein PLLC
Treat William M.
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