Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-09-27
2003-05-27
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C326S083000
Reexamination Certificate
active
06570414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to driver circuits, and more particularly to circuitry for reducing the crowbar current in high-speed driver circuits.
2. Description of the Related Art
Conventional high-speed driver circuits are wasteful due to the unnecessary power that is dissipated in driver transistors during signal transitions. To illustrate,
FIG. 1
is a schematic diagram of a conventional driver circuit
100
. Conventional driver circuit
100
is embodied in an integrated circuit (IC)
102
having an output pad
104
for coupling to a load, which is represented by a load capacitor
106
coupled to a ground
128
. A reference clock signal
108
is coupled to an input of an inverter gate
110
which has an output coupled to gates of driver transistors
118
and
124
. Driver transistor
118
, which is a P-channel type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), has a source coupled to a reference voltage
126
. Driver transistor
124
, which is an N-channel type MOSFET, has a source coupled to ground
128
.
An enable signal
112
is coupled to an input of an inverter gate
114
which has an output coupled to an input of an inverter gate
116
. Inverter gate
116
has an output coupled to gates of transistors
120
and
122
. Transistor
120
has a drain coupled to a drain of driver transistor
118
, whereas transistor
122
has a source coupled to a drain of transistor
124
. A source of transistor
120
is coupled to a drain of transistor
122
, which forms an output to output pad
104
.
When enable signal
112
is high, driver circuit
100
is enabled and transistors
120
and
122
are on. Reference clock signal
108
is inverted by inverter gate
110
and provided to driver transistors
118
and
124
, turning them on and off at the same time. Since the gate inputs to driver transistors
118
and
124
are common, there is a direct current path from reference voltage
126
to ground
128
in the middle of each clock signal transition. This current flows through driver transistor
124
when charging load capacitor
106
, and through driver transistor
118
when discharging load capacitor
106
. This wasted current is commonly referred to as “crowbar current.” The crowbar current not only increases the total power consumption of driver circuit
100
, but contributes to the total peak current which may create layout and Simultaneous Switching Noise (SSN) problems.
FIG. 2
is a schematic diagram of another conventional driver circuit
200
which is configured to somewhat reduce the crowbar current. Conventional driver circuit
200
has an output pad
204
for coupling to a load, which is represented by a load capacitor
206
coupled to a ground
224
. A reference clock signal
208
is coupled to a first input of a NAND gate
210
and to a first input of a NOR gate
216
. An output of NAND gate
210
is coupled to a delay circuit
226
, which has an output coupled to a gate of driver transistor
218
. An output of NOR gate
216
is coupled to a gate of driver transistor
220
. Driver transistor
218
is a P-channel type MOSFET which has a source coupled to a reference voltage
222
. Driver transistor
220
is an N-type MOSFET which has a source coupled to ground
224
and a drain coupled to a drain of driver transistor
218
. The latter connection forms an output coupled to output pad
204
. An enable signal
208
is coupled to a second input of NAND gate
210
and to an input of an inverter gate
214
which has an output coupled to a second input of NOR gate
216
.
When enable signal
212
is high, driver circuit
200
is enabled. A high voltage is maintained at the second input of NAND gate and a low voltage from the output of inverter gate
214
is maintained at the second input of NOR gate
216
. Reference clock signal
208
is provided to driver transistors
218
and
220
through NAND and NOR gates
210
and
216
, turning driver transistors
218
and
220
on and off at different times. Advantageously, delay circuit
226
delays the clock signal to driver transistor
218
so that the crowbar current is eliminated during off-to-on transitions at output pad
204
. However, there is still a direct current path from reference voltage
222
to ground
224
during on-to-off transitions at output pad
204
.
FIG. 3
is a schematic diagram of yet another conventional driver circuit
300
which is a variation of conventional driver circuit
200
of FIG.
2
. Conventional driver circuit
300
is the same as conventional driver circuit
200
of
FIG. 2
, except that conventional driver circuit
300
has a delay circuit
302
in the path to the gate of driver transistor
220
but not in the path to the gate of driver transistor
218
. Advantageously, delay circuit
302
delays the clock signal to driver transistor
220
so that the crowbar current is eliminated during on-to-off transitions at output pad
204
. However, there is still a direct current path from reference voltage
222
to ground
224
during off-to-on transitions at output pad
204
.
As described, even conventional driver circuits
200
and
300
configured to reduce the crowbar current reduce it on one edge only (rising or falling). Accordingly, there is a need for methods and apparatus to reduce or eliminate the crowbar current in driver circuits.
SUMMARY OF THE INVENTION
According to the present invention, a driver circuit includes a first driver transistor having a source coupled to a first reference voltage; a second driver transistor having a source coupled to a second reference voltage and a drain coupled to a drain of the first driver transistor; first logic gate circuitry having an input coupled to a reference clock signal and an output coupled to a gate of the first driver transistor; and second logic gate circuitry having an input coupled to the reference clock signal and an output coupled to a gate of the second driver transistor. The first logic gate circuitry produces a first clock input signal at its output and the second logic gate circuitry produces a second clock input signal at its output. The first clock input signal provides off-to-on transitions which precede off-to-on transitions provided by the second clock input signal and on-to-off transitions which succeed on-to-off transitions provided by the first clock input signal. Preferably, this signaling scheme is achieved by providing the first logic gate circuitry with a first input voltage threshold value that is sufficiently different from a second input voltage threshold value of the second logic gate circuitry. Advantageously, this prevents direct paths from the first reference voltage to the second reference voltage during both off-to-on and on-to-off transitions of the driver transistors.
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patent: 5751180 (1998-05-01), D'Addeo
patent: 5883527 (1999-03-01), Saito
patent: 5898320 (1999-04-01), Li et al.
patent: 5929694 (1999-07-01), Yanagawa et al.
patent: 5963047 (1999-10-01), Kwong et al.
patent: 5990705 (1999-11-01), Lim
patent: 6057717 (2000-05-01), Kawano et al.
patent: 6100727 (2000-08-01), Nomura
patent: 6218857 (2001-04-01), Sharpe-Geisler et al.
patent: 6236237 (2001-05-01), Wong et al.
patent: 6281706 (2001-08-01), Wert et al.
patent: 6281708 (2001-08-01), Kenny
Applied Micro Circuits Corporation
Callahan Timothy P.
Gray Cary Ware & Freidenrich
Meador Terrance A.
Nguyen Linh
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