Semiconductor device manufacturing: process – Semiconductor substrate dicing – With attachment to temporary support or carrier
Patent
1996-08-19
2000-03-21
Picardat, Kevin M.
Semiconductor device manufacturing: process
Semiconductor substrate dicing
With attachment to temporary support or carrier
438460, 438462, 438612, 438613, H01L 21301, H01L 2146, H01L 2178
Patent
active
060402350
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to methods and apparatus for producing integrated circuit devices and to integrated circuit devices produced thereby.
BACKGROUND OF THE INVENTION
An essential step in the manufacture of all integrated circuit devices is known as "packaging" and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
At present three principal technologies are employed for packaging semiconductors: wire bonding, tape automatic bonding (TAB) and flip chip.
Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto. The individual leads may be connected individually or as a group to the various bond pads on the chip.
Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be "flipped" circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.
The above-described technologies each have certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
The flip-chip does not provide packaging but rather only interconnection. The interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits the use of available substrates to silicon or materials which have thermal expansion characteristics similar to those of silicon.
SUMMARY OF THE INVENTION
The present invention seeks to provide apparatus and techniques for production of integrated circuit device overcome many of the above limitations and provide integrated circuits of relatively smaller size and weight and enhanced electrical performance.
There is thus provided in accordance with a preferred embodiment of the present invention a method for producing integrated circuit devices including the steps of: second planar surfaces, each of the integrated circuits including a multiplicity of pads; protective material; attached thereto, thereby to define notches along outlines of a plurality of prepackaged integrated circuit devices; devices while they are still joined together on the wafer, at least a portion of said metal contacts extending into the notches; and devices into individual devices.
Throughout the specification and claims, the terms "cutting" and "cut" shall have broader than usual meaning and shall refer to removal of material or separating along a line by any suitable technique, such as, for example, etching, sawing, sandblasting and milling.
It is noted that the term "waferwise" does not require that a whole wafer be so processed at a given time. "Waferwise" applies equally to steps applied to multiple dies prior to dicing thereof.
In accordance with a preferred embodiment of the present invention the step of partially cutting exposes sectional surfaces of the multiplicity of pads.
Preferably the step of partially cutting cuts pads so as to simultaneously define electrical contact regions for both of a pair of adjacent integrated circuits.
Additionally in accordance with a preferred embodiment of the present invention there is provided a method for producing integrated circuit devices including the steps of: integrated circuits including a multiplicity of pads; and outlines of a plurality of integrated circuit, and wherein the step of partially cuttin
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Picardat Kevin M.
Shellcase Ltd.
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