Methods and apparatus for predicting an underflow condition...

Details Methods and apparatus for predicting an underflow condition... Methods and apparatus for predicting an underflow condition...

2005-11-08

2005-11-08

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S501000

Reexamination Certificate

active

06963894

ABSTRACT:
Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. Preferably, the prediction is “pessimistic” in that it predicts that an underflow condition will result in all situations where an underflow condition might result. However, the methods and apparatus may also predict that an underflow condition might result in some situations where an underflow condition will not result. If an underflow condition is predicted, the floating-point multiply-add operation is preferably performed by a software routine capable of handling the underflow condition. If an underflow condition is not predicted, the floating-point multiply-add operation is preferably performed by a hardware circuit to increase speed and reduce computational overhead.

REFERENCES:
patent: 5257216 (1993-10-01), Sweedler
patent: 5548545 (1996-08-01), Brashears et al.
patent: 5550767 (1996-08-01), Taborn et al.
patent: 6631392 (2003-10-01), Jiang et al.
patent: 6633895 (2003-10-01), Bass et al.
Steve Hollasch, “IEEE Standard 754 Floating Point Numbers”, Dec. 4, 2001, http://research.microsoft.com/˜hollasch/cgindex/coding/ieeefloat.html.

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