Methods and apparatus for performing mathematical operations...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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10740086

ABSTRACT:
Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-integer value. The multiplier value is determined by extracting information from a first portion of a bitfield based on the scaled-integer value. The scale value is determined by extracting information from a second portion of the bitfield based on the scaled-integer value. The first and second portions of the bitfield are configurable to include signed integer values. The example method then performs an arithmetic operation based on the multiplier value and the scale value.

REFERENCES:
patent: 4603323 (1986-07-01), Hassitt et al.
patent: 6182100 (2001-01-01), Schmookler
patent: 6232894 (2001-05-01), Kawasaki
patent: 6516332 (2003-02-01), Carter
“IEEE Standard for Floating-point Arithmetic.” ANSI/IEEE Standard 754-1985, pp. 1-18. Published by The Institute of Electrical and Electronics Engineers, Inc., New York, New York. 1985.
Hollasch, S. IEEE Standard 754 Floating Point Numbers. pp. 1-6. [retrieved on Oct. 30, 2003]. Retrieved from the Internet: <URL: http://research.microsoft.com/˜hollasch/cgindex/coding/ieeefloat.html>.
Zadrozny, W., “Axiomatizations of Floating Point Arithmetics” Proceedings of the Symposium on Computer Arithmetic. Urbana, Jun. 4-6, 1985, Silver Spring IEEE Computer Society PR, US, vol. SYMP. 7, Jun. 4, 1985.
“16-Bit Floating-Point Math in an 8-Bit Microprocessor”, IBM Technical Disclosure Bulletin, IBM Corp. New York, US, vol. 32, No. 7, Dec. 1, 1989 (2 Pages).
C. Locke, “Scaled Arithmetic Macroinstructions”, IBM Technical Disclosure Bulletin, vol. 13, No. 12, May 1971 (1 Page).
K. Hwang, “Computer Arithmetic, Principles, Architecture, and Design” 1979 , Wiley & Sons, New York, NY, USA 120520, XP002325374, pp. 292-295, Figure 9.2 (4 Pages).
Seehyn Kim, et al., “A Floating-Point to Fixed-Point Assembly Program Translator for The TMS 320C25”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE INC. New York, US, vol. 41, No. 11, Nov. 1, 1994 (5 Pages).
Kim, et al., “A Floating-Point to Fixed-Point Asembly Program Translator”, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 41. No. 11 Nov. 1994. (5 Pages).
International Searching Authority, “International Search Report and the Written Opinion of the International Searching Authority, or the Declaration”, Mailed on May 25, 2005, (15 Pages).
International Preliminary Report on Patentability corresponding to International Application No. PCT/US2004/040361, Jun. 29, 2006, 9 pages.

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