Boots – shoes – and leggings
Patent
1986-12-01
1990-06-12
Shaw, Gareth D.
Boots, shoes, and leggings
36424342, 3642394, 3642543, 3642631, G06F 900, G06F 1300
Patent
active
049338374
ABSTRACT:
Methods and apparatus are set forth for optimizing the performance of instruction processors using an instruction cache memory in combination with a sequential transfer main memory. According to the invention, the memory system stores preselected instructions in cache memory. The instructions are those that immediately follow a branch operation. The purpose of storing these instructions is to minimize, and if possible, eliminate the delay associated with fetching the same sequence from main memory following a subsequent branch to the same instruction string. The number of instructions that need to be cached (placed in cache memory) is a function of the access time for the first and subsequent fetches from sequential main memory, the speed of the cache memory, and instruction execution time. The invention is particularly well suited for use in computer systems having RISC architectures with fixed instruction lengths.
REFERENCES:
patent: 3896419 (1975-07-01), Lange et al.
patent: 4313158 (1982-01-01), Porter et al.
patent: 4315312 (1982-02-01), Schmidt
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4442488 (1984-04-01), Hall
Advanced Micro Devices , Inc.
Eakman Christina M.
Shaw Gareth D.
LandOfFree
Methods and apparatus for optimizing instruction processing in c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for optimizing instruction processing in c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for optimizing instruction processing in c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-621962