Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2007-09-26
2008-10-14
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000, C327S147000
Reexamination Certificate
active
07436229
ABSTRACT:
A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
REFERENCES:
patent: 5559474 (1996-09-01), Matsumoto et al.
patent: 6317008 (2001-11-01), Gabara
patent: 6693496 (2004-02-01), Lebouleux
patent: 6828864 (2004-12-01), Maxim et al.
patent: 6927611 (2005-08-01), Rhee et al.
patent: 6967513 (2005-11-01), Balboni
patent: 7078946 (2006-07-01), van der Valk et al.
patent: 7162002 (2007-01-01), Chen et al.
patent: 7323916 (2008-01-01), Sidiropoulos et al.
Sidiropoulos et al., Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers, 2000 Symposium on VLSI Circuits Digest of Technical Papers.
Mansuri et al., A Low-Power Low-Jitter Adaptive-Bandwidth PLL and Clock Buffer, ISSCC 2003/Session 24/Clock Generation/Paper 24.5, ISSCC 2003/Feb. 12, 2003/Salon 8/ 3:45PM, 2003 IEEE International Solid-State Circuits Conference.
Mansuri et al. Jitter Optimization Based On Phase-Locked Loop Design Parameters, IEEE Journal Of Solid-State Circuits, vol. 37, No. 11, Nov. 2002.
Maxim et al., A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-μm CMOS PLL Based on a Sample-Reset Loop Filter, IEEE Journal Of Solid-State Circuits, vol. 36, No. 11, Nov. 2001.
Maneatis, Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL, IEEE Journal Of Solid-State Circuits, vol. 38, No. 11, Nov. 2003.
Sidiropoulos, A Semidigital Dual Delay-Locked Loop, IEEE Journal Of Solid-State Circuits, vol. 32, No. 11, Nov. 1997.
Acharya Nikhil
Liu Dean
Loinaz Marc
Narayanaswami R. Shekhar
Sidiropoulos Stefanos
Le Dinh T.
Net Logic Microsystems, Inc.
Stattler-Suh PC
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