Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1998-10-09
2000-12-26
Eng, David Y.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
G06F 1516
Patent
active
061675016
ABSTRACT:
Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
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Barry Edwin F.
Drabenstott Thomas L.
Morris Grayson
Pechanek Gerald G.
Pitsianis Nikos P.
Billions of Operations Per Second, Inc.
Eng David Y.
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