Boots – shoes – and leggings
Patent
1990-10-26
1993-03-09
Dixon, Joseph L.
Boots, shoes, and leggings
395400, 364DIG1, G06F 1200, G06F 1300
Patent
active
051931702
ABSTRACT:
Methods and apparatus for maintaining cache integrity in a computing system that includes a central processing unit (CPU), Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between said CPU, RAM and ROM, wherein said computing system is capable of supporting a ROM mapped to RAM mode of operation, and further wherein said local memory controller, whenever said ROM mapped to RAM mode is enabled, (1) implements a snoop cycle to detect CPU write ROM operations and, upon detecting such an operation, (2) provides a cache invalidation signal to the CPU. The CPU utilizes the invalidation signal, along with the invalidation address on the local bus coupling the CPU and memory controller, to invalidate any cache data entry corresponding to the main memory address targeted by the CPU write ROM operation. The invalidation takes place while the write operation is in progress.
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patent: 5091846 (1992-02-01), Sachs et al.
patent: 5091850 (1992-02-01), Culley
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
80486 Microprocessor, Intel Corporation, Apr. 1989, pp. 80, 81, 83, pp. 116 and 117.
Asta Frank J.
Dixon Joseph L.
International Business Machines - Corporation
Terrile Stephen A.
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