Methods and apparatus for interleaving memory transactions into

Details Methods and apparatus for interleaving memory transactions into Methods and apparatus for interleaving memory transactions into

1994-03-28

1996-06-25

Rudolph, Rebecca L.

Boots, shoes, and leggings

39542102, 364DIG1, G06F 1200

Patent

active

055308376

ABSTRACT:
Methods and apparatus are provided for interleaving memory transactions into an arbitrary number of memory banks that need not be equal size. A memory address range is divided into subranges of contiguous addresses. A first embodiment associates the subranges to a unique set of banks. Memory transactions falling within a subrange are interleaved among banks associated with the subrange. A second embodiment associates a set of banks with each subrange. The set of banks of one subrange are not necessarily independent of the set of banks of a second subrange. A third embodiment is a hybrid of the first and second embodiment. Range detection mechanisms are provided for detecting if a memory transaction falls within a subrange. In addition, an ID number is produced from the memory address according to an interleaving algorithm. The ID number is compared to bank ID numbers associated with each of the banks. If the ID matches the bank ID and the address falls within a corresponding subrange the bank is selected to receive the memory transaction. Lastly, a mechanism is provided for producing a unique bank offset from the memory address.

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"The Cydra 5 Stride-Insensitive Memory System" 1989 International Conference on Parallel Processing, pp. I-242-I-246, B. Ramakrishna Rau, Michael S. Schlansker, Eavid W. L. Yen.

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