Methods and apparatus for indirect VLIW memory allocation

Data processing: software development – installation – and managem – Software program development tool – Testing or debugging

Reexamination Certificate

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C717S151000, C717S152000, C717S161000, C712S209000

Reexamination Certificate

active

09886855

ABSTRACT:
Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.

REFERENCES:
patent: 5442790 (1995-08-01), Nosenchuck
patent: 5790858 (1998-08-01), Vogel
patent: 5848255 (1998-12-01), Kondo
patent: 5930508 (1999-07-01), Faraboschi et al.
patent: 6044450 (2000-03-01), Tsushima et al.
patent: 6175948 (2001-01-01), Miller et al.
patent: 6305014 (2001-10-01), Roediger et al.
patent: 6367076 (2002-04-01), Imai et al.
patent: 6457173 (2002-09-01), Gupta et al.
patent: 6507947 (2003-01-01), Schreiber et al.
patent: 6598221 (2003-07-01), Pegatoquet et al.
patent: 6647547 (2003-11-01), Kanamaru et al.
patent: 6651247 (2003-11-01), Srinivasan
patent: 6658551 (2003-12-01), Berenbaum et al.
patent: 6675380 (2004-01-01), McKinsey et al.
patent: 6735690 (2004-05-01), Barry et al.
patent: 6738893 (2004-05-01), Rozas
patent: 6748589 (2004-06-01), Johnson et al.
patent: 6754893 (2004-06-01), Granston et al.
patent: 6772414 (2004-08-01), Roediger et al.
patent: 2002/0112228 (2002-08-01), Granston et al.
patent: 2003/0200420 (2003-10-01), Pechanek et al.
Diwan et al., Memory system performance of programs with intensive heap allocation, Aug. 1995, ACM Transactions on Computer Systems (TOCS), vol. 13 Issue 3, pp. 1-30.
Marcelo et al., Cache performance of fast-allocating programs, Oct. 1995, Proceedings of the seventh international conference on Functional programming languages and computer architecture, pp. 1-13.
Suhyun et al., Unroll-based register coalescing, May 2000, Proceedings of the 14th international conference on Supercomputing, pp. 1-10.
Chaitin, Register Allocation & Spilling via graph Coloring, ACM, 1982, pp. 98-105.
Eichenberger et al., Register allocation for predicted code, IEEE, Dec. 1995 pp. 180-191.
Muresan et al., Current consumption dynamics at instruction and program level for a VLIW DSP processor, IEEE, 2001, pp. 130-135.
Zalamea et al., Modulo scheduling with integrated register spilling for clustered VLIW architectures, IEEE, 2001 pp. 160-169.

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