Methods and apparatus for improving processing performance...

Details Methods and apparatus for improving processing performance... Methods and apparatus for improving processing performance...

2008-07-01

2008-07-01

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Architecture based instruction processing

Reexamination Certificate

active

11079565

ABSTRACT:
Methods and apparatus provide for performing pre-execution processes to prepare instructions of an instruction set for further processing; executing the instructions in a pipeline of execution stages using digital logic for processing data in accordance with the instructions within one clock cycle per stage; latching the data each clock cycle for delivery to a next execution stage using one or more of a plurality of latch point circuits; and controlling each of the latch point circuits to operate as a buffer or as a latch.

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Office Action in corresponding JP Patent Application No. 2006-061086, dated Sep. 12, 2006, 3 pgs.

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