Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2006-04-25
2006-04-25
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Reexamination Certificate
active
07035997
ABSTRACT:
In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the cache or a branch will be taken. The prediction or predictions are used by the fetch algorithm in determining from which stream to fetch. In some cases probabilities are determined and also used in decisions, and predictors may be used at either or both of fetch and dispatch stages.
REFERENCES:
patent: 4197579 (1980-04-01), Forsman et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 5309173 (1994-05-01), Izzi et al.
patent: 5361337 (1994-11-01), Okin
patent: 5461722 (1995-10-01), Goto
patent: 5511210 (1996-04-01), Nishikawa et al.
patent: 5535365 (1996-07-01), Barriuso et al.
patent: 5542088 (1996-07-01), Jennings, Jr. et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5600837 (1997-02-01), Artieri
patent: 5649144 (1997-07-01), Gostin et al.
patent: 5694572 (1997-12-01), Ryan
patent: 5701432 (1997-12-01), Wong et al.
patent: 5713038 (1998-01-01), Motomura
patent: 5745778 (1998-04-01), Alfieri
patent: 5748468 (1998-05-01), Notenboom et al.
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5784613 (1998-07-01), Tamirsa
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5815733 (1998-09-01), Anderson et al.
patent: 5852726 (1998-12-01), Lin et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5867725 (1999-02-01), Fung et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5933627 (1999-08-01), Parady
patent: 5946711 (1999-08-01), Donnelly
patent: 5987492 (1999-11-01), Yue
patent: 6016542 (2000-01-01), Gottlieb et al.
patent: 6018759 (2000-01-01), Doing et al.
patent: 6029228 (2000-02-01), Cai et al.
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6115802 (2000-09-01), Tock et al.
patent: 6119203 (2000-09-01), Snyder et al.
patent: 6192384 (2001-02-01), Dally et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6260077 (2001-07-01), Rangarajan et al.
patent: 6308261 (2001-10-01), Morris et al.
patent: 6356996 (2002-03-01), Adams
patent: 6430593 (2002-08-01), Lindsley
patent: 6442675 (2002-08-01), Derrick et al.
patent: 6487571 (2002-11-01), Voldman
patent: 6493749 (2002-12-01), Paxhia et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 2002/0062435 (2002-05-01), Nemirovsky et al.
patent: 2003/0084269 (2003-05-01), Drysdale et al.
patent: 806730 (1997-11-01), None
patent: 827071 (1998-03-01), None
patent: 2103630 (1988-10-01), None
patent: 63254530 (1988-10-01), None
patent: 4335431 (1992-11-01), None
patent: 546379 (1993-02-01), None
patent: 09-506752 (1997-06-01), None
patent: 10-11301 (1998-01-01), None
patent: 10-124316 (1998-05-01), None
patent: 10-207717 (1998-08-01), None
patent: WO 9427216 (1994-11-01), None
patent: WO0023891 (2000-04-01), None
Yamamoto, Wayne, “An Analysis of Multistreamed, Superscalar Processor Architectures”, University of CA, Santa Barbara dissertation, Dec. 1995, Santa Barbara Ca.
Steere et al, “A Feedback-Driven Proportion Allocator for Real Estate Scheduling”, Third Symposium on Operating Systems Design and Implementation, Feb. 1999, pp. 145-158, USENIX Association.
Yamamoto, Wayne, et al., “Increasing Superscalar Performance Through Multistreaming”, 1995.
Tullsen, Dean, et al., “Stimultaneous Multithreading: Maximizing on-Chip Parallelism”, 22ndAnnual International Symposium on Computer Architecture, Jun. 1995, Santa Margherita, Ligure, Italy.
Yoaz et al., “Speculation Techniques for Improving Load Related Instruction Scheduling”, 1999, pp.42-53, IEEE.
Kessler, R.E., “The Alpha 21264 Microprocessor: Out-of-Order Execution at 600 Mhz”, Aug. 1998.
Tullsen, et al., Supporting Fine-Grained synchronization on a Simultaneous Multithreading Processor, UCSD CSE Technical Report CS98-587, Jun. 1998, all pages, US.
Nemirovsky et al., “Quantitative Study of Data Caches on a Multistreamed Architecture”, Workshop on Multithreaded Execution Architecture and Compilation, Jan. 1998.
Ll et al, “Design and Implementation of a Multiple-Execution-Pipeline Architecture”, 7thInternational Conference on Parallel and Distributed Computing and Systems, Oct. 1995.
Donaldson et al., “DISC: Dynamic Instruction Stream Computer, An Evaluation of Performance”, 26thHawaii Conference on Systems Sciences, 1993, pp. 448-456, vol. 1.
Nemirovsky et al., DISC: Dynamic Instruction Stream Computer ACM, 1991, pp.163-171.
Yamamoto, Wayne et al, “Performance Estimation of Multistreamed, Superscalar PRocessors”, IEEE, 1994, pp. 195-204, Hawaii, US.
Gruenwald, et al., “Towards Extremely Fast Context Switching in a Block-Multithreaded Processor”, Proceedings of Euromicro-22, 1996, pp. 592-599.
Bradford, Jeffrey et al., “Efficient Synchronization for Multithreaded Processors”, Workshop on Multithreaded Execution, Architecture and Compilation, Jan. -Feb. 1998, pp. 1-4.
“The PowerPC Architecture: A Specification for a New Family of RISC Processors”, Second Edition, May 1994, pp.70-72, Morgan Kaufmann, San Francisco.
MC68020 32-Bit Microprocessor User's Manual, Third Edition, 1989, pp3-125, 3-126, and 2-127, Prentice Hall, New Jersey.
Potel, M.J., “Real-time Playback in Animation Systems”, Proceedings of the 4thAnnual Conference on Computer Graphics and Interactive Techniques, 1977, pp.72-77, San Jose, Ca.
Arm Architecture Reference Manual, 1996, pp.3-41, 3-42, 3-43, 3-67, 3-68, Prentice Hall.
ESA/390 Principles of Operation, IBM Library Server, 1993, Table of Contents and Para. 7.5.31 and 7.5.70 (available at http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOK/DZ(AR001/CONTENTS).
MC8810 Second Generation RISC Microprocessor User's Manual, 1991, pp. 10-66, 10-67, and 10-71, Motorola, Inc.
Difendorff, Keith et al., Organization of the Motorola 88110 Superscalar RISC Microprocessor, IEEEE Micro, Apr. 1992, pp.40-63, vol. 12, No. 2.
Kane, Gerry, PA-RISC 2.0 Architecture, 1996, pp.7-106 and 7-107, Prentice hall, New Jersey.
Difendorff, Keith et al., “AltiVec Extension to PowerPC Accelerates Media Processing”, Mar. -Apr. 2000, pp.85-95, IEEE Micro, vol. 20, No. 2.
Pai, Vijay et al., “An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors”, Proceedings of ASPLOS VII, Oct. 1996, pp. 12-23, ACM, Inc.
Fiske et al., “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors”, 1995, pp.210-211, IEEE.
Cui et al., Parallel Replacement Mechanism for MultiThread, Advances in Parallel and Distributed Computing, 1997. Proceedings, IEEE, Mar. 21, 1977, pp. 338-344.
Tullsen et al., Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, USCD CSE Technical Report CS 98-587, Jun. 1998, all pages, US.
Thekkath et al. The Effectiveness of Multiple Hardware Contexts. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems pp. 328-337, San Jose Ca, Oct. 1994. ACM.
McFarling, Scott. Combining Branch Predictors. WRL Technical Note TN-36. Jun. 1993. Pages 11-12. Digital Western Research Laboratory. Palo Alto, Ca, US.
U.S. Appl. No. 09/592,106, Melvin et al., filed Jun. 12, 2000.
U.S. Appl. No. 09/595,776, Musoll et al., filed Jun. 16, 2000.
U.S. Appl. No. 09/616,385, Musoll et al., filed Jul. 14, 2000.
U.S. Appl. No. 09/629,805, Nemirovsky et al., filed Jul. 31, 2000.
U.S. Appl. No. 09/312,302, Nemirovsky et al., filed May 15, 1999.
U.S. Appl. No. 09/273,810, Nemirovsky et al., filed Mar. 22, 1999.
U.S. Appl. No. 09/240,012, Nemirovsky et al., filed Jan. 27, 1999
Musoll Enric
Nemirovsky Mario
Boys Donald R.
Coleman Eric
Huffman James W.
MIPS Technologies Inc.
LandOfFree
Methods and apparatus for improving fetching and dispatch of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for improving fetching and dispatch of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for improving fetching and dispatch of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3600404