Methods and apparatus for improved phase linearity in a...

Oscillators – Ring oscillators

Reexamination Certificate

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C331S045000, C331S074000, C327S258000, C327S361000

Reexamination Certificate

active

07808329

ABSTRACT:
Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

REFERENCES:
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patent: 7577225 (2009-08-01), Azadet et al.
patent: 7602257 (2009-10-01), Schrom et al.
patent: 2008/0231376 (2008-09-01), Kinoshita et al.
patent: 2009/0215423 (2009-08-01), Hwang et al.
Bult et al., “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” IEEE Journal of Solid-State Circuits, vol. 32, No. 12, pp. 1887-1895 (Dec. 12, 1997).
Chou et al., “Phase Averaging and Interpolation Using Resistor Strings or Resistor Rings for Multi-Phase Clock Generation,” IEEE Transactions on Circuits and Systems—I, Regular Papers, vol. 53, No. 5, pp. 984-991 (May 5, 2006).

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