Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Controlling current distribution within bath
Reexamination Certificate
2002-08-08
2004-11-02
Valentine, Donald R. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Controlling current distribution within bath
C204S22400M, C204SDIG007, C205S123000, C205S137000
Reexamination Certificate
active
06811669
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to methods and apparatus for electroplating or electrochemical deposition during metal layer deposition in the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor products, individual electrical devices are formed on or in a semiconductor substrate. Thereafter, interconnect processing is performed wherein the electrical devices are interconnected to form electrical circuits. Typically, a multi-level interconnect network is fabricated in layers formed over the electrical devices, by which the device active elements are connected to one another to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching cavities such as vias and trenches therein.
Conductive material, such as copper is then deposited into the cavities and the wafer is planarized using chemical mechanical polishing (CMP) to form an interconnect structure. Typical interconnect structures are fabricated using single or dual damascene processes in which trenches and vias are formed (e.g., etched) in a dielectric layer. Copper is then deposited into the trenches and vias and over the insulative layer, followed by CMP planarization to leave a copper wiring pattern inlaid within the dielectric layer trenches and vias. The process is then repeated to form further interconnect layers or levels as needed by which the desired circuit interconnections are made in a multi-level interconnect network.
Diffusion barriers are often formed in the damascene cavities prior to deposition of copper to prevent or reduce diffusion of copper into the dielectric material. Such barriers are typically formed using conductive compounds of transition metals such as tantalum nitride, titanium nitride, and tungsten nitride as well as the various transition metals themselves. Conductive metals, such as aluminum, copper, or the like are then used to fill the cavities after barrier layer formation, where copper is gradually replacing aluminum to improve the conductivity of the interconnect circuits.
The deposition of the conductive copper material in such interconnect processing is generally performed by electroplating, as illustrated in
FIGS. 1A-2
. This type of processing is sometimes referred to as electrochemical deposition (ECD), and is performed in an electroplating system
2
, sometimes referred to as an ECD reactor. In this case, a conductive (e.g., copper) seed layer (not shown) is first formed on a wafer
10
after the diffusion barrier formation, typically via chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques. In subsequent plating in the system
2
, the wafer
10
is electrically coupled with a cathode/wafer holder
4
in a reactor chamber or reservoir
6
filled with electrolytic fluid. The fluid is injected into the reservoir
6
through an inlet port
8
, and extracted through an exit port
12
.
A voltage is applied across the cathode/wafer holder
4
and an anode
14
via a power source or supply
18
to establish an electric field
16
(e.g.,
FIG. 1B
) in the plating fluid, causing migration and deposition of copper to the wafer workpiece
10
at the wafer holder
4
, wherein the wafer
10
operates as a cathode during the plating operation through connection to the wafer holder
4
. The initial seed layer thus provides a conductive surface on the wafer
10
such that the electrical connection thereof to the cathode wafer holder
4
causes the electric field lines to end at the wafer
10
. The system
2
may further include an anode filter
14
a
to prevent collection of particulate matter on the cathode
4
, which itself is typically fabricated of copper. As illustrated in
FIG. 2
, the system
2
may further include a fluid dispersion disk
20
with spirally disposed holes
22
to direct the electrolytic plating fluid to the wafer
10
in a controlled fashion.
In a typical ECD process, the plated upper surface of the wafer
10
is located so as to face the anode
14
in the reservoir. The wafer holder structure
4
electrically contacts the plated upper wafer surface at the peripheral edges
10
a
thereof. However, because the seed layer is of finite thickness, a non-zero resistance exists between interior points
10
b
on the plated wafer surface and the edge points
10
a
at which electrical contact is made to the cathode wafer holder clamp
4
. The seed layer thus has a non-uniform voltage potential which is positive at the center
10
b
and negative at the wafer edges
10
a
, resulting in higher current densities near the wafer edge
10
a
than at the center
10
b
, particularly at the beginning of the plating process.
The rate of copper deposition during electroplating at a given point on the wafer surface is generally proportional to the current density thereat. Thus, the deposited copper from the ECD process is thinner at the center
10
b
than at the edges
10
a
, due to the seed layer resistance. This is illustrated in a graph
30
in
FIG. 1B
of deposited copper thickness (y axis) versus position (x axis), wherein the curve
32
has a concave profile. Although subsequent copper deposition in the ECD reservoir
6
reduces this resistance disparity, the initial electrode-position rate in particular is higher at the edges
10
a
than at the interior
10
b
of the wafer
10
. Thus, the initial deposition causes a concave copper thickness profile
32
, which is built up even when the inner and outer deposition rates become closer.
Recent scaling efforts in semiconductor devices have resulted in smaller feature sizes and closer feature spacing. Seed layer thicknesses continue to be reduced accordingly, to avoid necking effects and other problems in filling the gaps between such closely spaced features. As a result, the initial seed layer resistance between the wafer center
10
b
and the edges
10
a
continues to increase due to seed layer thinning, thereby worsening the copper deposition uniformity problem. In addition, wafer sizes are increasing, for example, from 200 mm to newer 300 mm diameter wafers. This causes higher voltage drops between the wafer center
10
b
and edges
10
a
for a given seed layer thickness and resistivity. Thus, adjustment in the seed layer deposition process step has limited impact on combating the non-uniform deposited copper thickness in interconnect process steps employing electroplating.
Furthermore, conventional CMP processes often suffer from dishing and/or erosion difficulties, wherein material is removed in a non-uniform manner. For example, a CMP process may remove more material from the center
10
b
of the wafer
10
than from the edges
10
a
, thereby compounding the ECD deposition non-uniformities. Thus, the ECD process provides thick copper at the edges
10
a
and thin copper at the center
10
b
, after which the wafer
10
is planarized by CMP processing which removes material from the (thin) center
10
b
faster than from the (thick) edges
10
a.
While CMP process chemistry and other parameters may be adjusted to reduce material removal non-uniformities, it is generally desirable to provide an electroplating process by which a copper layer of uniform or controllable thickness is deposited prior to CMP processing. Absent such, current efforts include depositing more copper (e.g., lengthening the electroplating process) to ensure complete filling of the thin inner regions
10
b
of the wafer with sufficient process margin to compensate for the faster CMP removal rate at the center
10
b
. The CMP planarization, in turn, must be performed for longer periods of time to ensure exposure of dielectric material between the filled trenches at the edges
10
a
of the wafer
10
. Both such process refinements result in a net increase in processing time per wafer (e.g., and thus reduced throughput), which is undesirable.
Furthermo
Gonzalez, Jr. David
Losey Matthew W.
Brady III W. James
Keagy Rose Alyssa
Valentine Donald R.
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