Methods and apparatus for implementing bit-by-bit erase of a...

Details Methods and apparatus for implementing bit-by-bit erase of a... Methods and apparatus for implementing bit-by-bit erase of a...

2011-03-15

2011-03-15

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185280, C365S185290, C365S185330, C365S185110, C365S185050

Reexamination Certificate

active

07907450

ABSTRACT:
A NAND memory device is constructed using Silicon On Insulator (SOI) techniques. In particular, Thin Film Transistor (TFT) techniques can be used to fabricate the NAND Flash memory device. In both SOI and TFT structures, the body, or well, is isolated. This can be used to enable a bit-by-bit programming and erasing of individual cells and allows tight control of the threshold voltage, which can enable MLC operation.

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