Methods and apparatus for implementing a saturating multiplier

Details Methods and apparatus for implementing a saturating multiplier Methods and apparatus for implementing a saturating multiplier

2004-08-12

2009-02-03

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S620000

Reexamination Certificate

active

07487196

ABSTRACT:
Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier.

REFERENCES:
patent: 5644519 (1997-07-01), Yatim et al.
patent: 6564238 (2003-05-01), Kim et al.
patent: 2003/0014457 (2003-01-01), Desai et al.
patent: 2004/0167954 (2004-08-01), Griessing
patent: 2005/0027773 (2005-02-01), Machnicki et al.
Rose et al, “Segmented Arithmetic Operators for Graphics Processing”, E577, Computer Arithmetic, Oregon State University, Fall 2003, pp. 1-7.

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