Methods and apparatus for implementing a pseudo-LRU cache memory

Details Methods and apparatus for implementing a pseudo-LRU cache memory Methods and apparatus for implementing a pseudo-LRU cache memory

1992-04-29

1994-10-04

Robertson, David L.

Boots, shoes, and leggings

364DIG1, 36424341, 36424613, 3642468, G06F 1314

Patent

active

053534255

ABSTRACT:
In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit. By providing that the process controls the state of the lock bits, the intelligence and knowledge the process contains regarding the frequency of use of certain memory locations can be utilized to provide a more efficient cache.

REFERENCES:
patent: 5029072 (1991-07-01), Moyer et al.
patent: 5249286 (1993-09-01), Alpert et al.
U.S. Patent Application, Ser. No.: 07/875,356, Filed: Apr. 29, 1992 Title: Cache Set Tag Array Inventors: Adam Malamy, et al. (Our Reference: 82225.P332).
Daryl Odnert et al., "Architecture And Compiler Enhancements For PARISC Workstations", 36th IEEE Computer Society International Conference, Feb. and Mar. 1991, pp. 214-218.

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