Methods and apparatus for implementing a power down in a...

Details Methods and apparatus for implementing a power down in a... Methods and apparatus for implementing a power down in a...

2006-07-18

2006-07-18

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Powering

C365S227000, C365S228000

Reexamination Certificate

active

07079441

ABSTRACT:
A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device, generating a second signal for causing the data strobe signal to remain in a predetermined state, and generating a third signal for preventing the data strobe signal in the predetermined state from being supplied as an output of the memory device.

REFERENCES:
patent: 5905688 (1999-05-01), Park
patent: 6744687 (2004-06-01), Koo et al.

Affiliated with

Also associated with

Rating

Methods and apparatus for implementing a power down in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for implementing a power down in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for implementing a power down in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3552203