Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2006-08-21
2010-06-29
Thai, Luan C (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S108000, C438S975000, C257S777000, C257SE23179
Reexamination Certificate
active
07745301
ABSTRACT:
Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude.
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Fish & Richardson P.C.
Terapede, LLC
Thai Luan C
LandOfFree
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