Methods and apparatus for fast check of floating point zero or n

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3647481, G06F 752

Patent

active

058620664

ABSTRACT:
Apparatus for performing floating point divide operations includes a divider and a comparator. The divider performs a floating point divide operation on a floating point numerator and a floating point denominator. The comparator performs a comparison of the floating point denominator, except for a sign bit of the floating point denominator, with a floating point value of 0.0. A logic element, responsive to a control signal indicative of the floating point divide operation, provides to the comparator equal sign bits associated with the floating point denominator and the floating point value of 0.0. A result of the comparison indicates a divide by zero operation and is independent of the sign of the floating point denominator. The result of the comparison is used to determine a course of action before the divide operation is completed.

REFERENCES:
patent: 4878189 (1989-10-01), Kawada
patent: 4961161 (1990-10-01), Kojima
patent: 5561619 (1996-10-01), Watanabe et al.
patent: 5638312 (1997-06-01), Simone

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