Methods and apparatus for error correction

Details Methods and apparatus for error correction Methods and apparatus for error correction

1997-06-26

1999-03-23

Baker, Stephen M.

Excavating

36472501, 3647461, H03M 1300

Patent

active

058870067

ABSTRACT:
An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. The error transform calculator includes a plurality of error transform processing circuits. The error transform calculator uses multiplexors to provide an adaptive input mechanism that adapts to receive known error transforms in an appropriate one of the error transform processing circuits. The multiplexors are used to form appropriate shift and feedback paths that are adapted to calculate unknown error transforms from the received known error transforms. The calculations are performed using multipliers and adders. Memory elements that store coefficients of a standard error locator polynomial are also used. An AND gate path is formed by coupling a plurality of AND gates in series. The AND gate path is used to provide simple and efficient control of the error transform calculator using coefficients of the standard error locator polynomial. An adaptive trigger circuit is provided to coordinate triggering of the inverse error transform calculator with the particular configuration used by the error transform calculator to perform calculations.

REFERENCES:
patent: 4868828 (1989-09-01), Shao et al.
patent: 5323402 (1994-06-01), Vaccaro et al.
Shao et al., "A VLSI Design of a Pipeline Reed-Solomon Decoder", IEEE Transactions on Computers, vol. C-34, No. 5, May 1985, pp. 393-403.

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