Methods and apparatus for dynamic instruction controlled...

Details Methods and apparatus for dynamic instruction controlled... Methods and apparatus for dynamic instruction controlled...

2004-04-19

2009-08-25

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C711S170000, C708S496000

Reissue Patent

active

RE040883

ABSTRACT:
A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.

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