Methods and apparatus for distributed processing and rapid ASIC

Details Methods and apparatus for distributed processing and rapid ASIC Methods and apparatus for distributed processing and rapid ASIC

1996-07-17

2000-06-06

Follansbee, John A.

G06F 1122

Patent

active

060729449

ABSTRACT:
The invention provides a distributed processing system having a host processor and one or more object oriented processors which are embodied as discrete components and as a collection of components on a single ASIC chip. A high level command language and a communications bus system are also provided both for use with discrete components and as an integral part of an ASIC chip. The ASIC chips are premanufactured to operate identically to a corresponding collection of discrete components. A distributed processing system is developed by coupling a collection of discrete object oriented processors and a host processor to a bus and writing a command language script to define the functionality of the system. After the system is designed and tested using discrete components, a suitable premanufactured ASIC or collection of ASICs is chosen and coupled to a host processor. The high level command language script permits the host processor and the ASIC system to perform identically to the discrete component system. An addressing scheme is provided in the command language such that multiple object orient processors may be given a single simultaneous command. Object oriented processors may have child ports with soft addressability to which other object oriented processors may be coupled. The child ports with soft addressability have software assignable addresses.

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